AY2017/2018 Semester 1
Faculty of Engineering
National University of Singapore
- Use
Midicsv.exeto convert a.midmusic file format to a.csvfile containing human-readable information about the music. - Use
midi_note_frequency_coe_generator.jsto generate the.coefile used by Verilog program to decide the frequency of all MIDI notes.
This is a first course that introduces fundamental digital logic, digital circuits, and programmable devices. The course also provides an overview of computer systems. This course provides students with an understanding of the building blocks of modern digital systems and methods of designing, simulating and realizing such systems. The emphasis of this module is on understanding the fundamentals of digital design across different levels of abstraction using hardware description languages.
5
- Lecture: 3 hrs
- Tutorial: 1 hrs
- Lab: 2 hrs
- Project: 2 hrs
- Preparation: 4 hrs
15-11-2017 10:00 AM
- Labs
- Project
- Midterm Quiz
- Final Quiz