static-timing-analysis

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

verilog semiconductor-physics genus custom-layout virtuoso digital-logic-design static-timing-analysis vlsi-design asic-design rtl-design innovus standard-cells eda-tools rtl-verification cmos-design rtl-to-gdsii cadence-tools

Updated Jul 12, 2025
Verilog

Circuits-and-Systems-Lab-CASlab / UPSET

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UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

fault-tolerance electronic-design-automation static-timing-analysis fault-analysis single-event-transient

Updated Feb 19, 2026
Verilog

Randy1005 / Ink

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Incremental k-Critical Path Generation

graph static-timing-analysis

Updated Jul 4, 2026
C++

MalakSadek / StaticTimingAnalyzer

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A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

python c html json graph-algorithms scl verilog logic-gates verilog-hdl logic-circuit static-timing-analysis

Updated Mar 25, 2021
HTML

kanndil / PathView

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An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

eda primetime critical-path-analysis pathview static-timing-analysis opensta schematic-layout electronic-design

Updated Oct 22, 2024
HTML

coherent17 / NYCU-Special-Topics-in-Computer-Aided-Design

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CAD in NYCU

quine-mccluskey-algorithm static-timing-analysis power-analyzer mix-signal-simulation

Updated Dec 22, 2023
Verilog

MaxTern-cyber / Synthesis_project

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Open-source EDA × AI for chip design. Graph-native, local-first tools for STA, GPU-parallelism, and hardware security.

graph-algorithms eda networkx rtl verilog dag netlist vlsi-physical-design networkx-graph hackathon-project netlist-parser hardware-verification static-timing-analysis vlsi-design gnn buildathon streamlit

Updated May 16, 2026
HTML

Ritvik2103 / microprocessor-design

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Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite

vivado logic-synthesis verilog-hdl static-timing-analysis

Updated Dec 7, 2024
Verilog

Uttejvluda / ECE-Roadmap

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A Roadmap application for ECE students from NIT college student based knowledge

roadmap skills vlsi ece vlsi-physical-design vlsi-circuits static-timing-analysis physical-design vlsi-design roadmaps physical-design-automation analog-layout design-for-test roadmap-sh roadmap-project ece-project

Updated Jan 29, 2026
JavaScript

SilviaB24 / DLX-Processor-Portfolio

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Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

vhdl vlsi risc-processor static-timing-analysis physical-design asic-design synopsys-dc cadence-innovus

Updated Dec 19, 2025

Zhungg / riscv-alu8-openlane

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Signed-off 8-bit RISC-V-style ALU from SystemVerilog RTL to GDSII using OpenLane 2.3.10 and SKY130A.

asic systemverilog alu risc-v static-timing-analysis physical-design openroad openlane sky130 rtl-to-gdsii

Updated Jul 22, 2026
SystemVerilog

gargihosmani / timingdiff

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An interactive git diff for VLSI timing signoff; visually compares two STA reports before and after a design change, instantly showing which paths sped up, slowed down, or newly violated timing.

python asic eda vlsi static-timing-analysis timing-closure hardware-design chip-design open-sta