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spunkycurative/README.md

Hi, I'm Shreya Sharma 👋

🔧 B.Tech ECE Student | Aspiring RTL / Design Verification Engineer | Digital Electronics & VLSI Enthusiast

Welcome to my GitHub profile! I’m passionate about RTL design, SystemVerilog, and VLSI verification, and I use this space to showcase my projects, experiments, and learning journey.

🌟 About Me

  • 🎓 Electronics & Communication Engineering student
  • 💻 Hands-on with Verilog, SystemVerilog, Testbenches, RTL Design
  • 📈 Exploring protocols (FIFO, UART, SPI, I2C, APB, AXI)
  • 📊 Interested in Digital Design, RTL Verification & VLSI
  • ✍️ Also a published poet (Whispers Within)

🛠️ Tech Stack

  • Languages: Verilog, SystemVerilog
  • Tools: EDA playground
  • Domains: Digital Electronics, RTL Design, Verification

📂 Featured Projects

Here are some of the projects I’ve worked on:

  • 🔸Verilog Basics → Adders, Multiplexers, Encoders, Flip-Flops, Counters, Registers, FIFO
  • 🔸UART Protocol → TX/RX design with baud rate generator and testbench
  • 🔸SPI Protocol → SPI Master–Slave design & verification
  • 🔸I2C Protocol → I2C Master Slave (Read/Write operations with testbench)
  • 🔸Axi-Lite protocol → Register-based communication with 5-channel handshake
  • 🔸Fifo Architecture → Synchronous FIFO (Single Clock with flags and testbench)

📌 Current Focus

  • Deep dive into SystemVerilog & UVM for Verification
  • Preparing for Design Verification internships
  • Expanding protocol-level projects (UART, SPI, I2C, AXI, APB)

✨ Fun Fact

When I’m not coding RTL or debugging testbenches, I write poetry and explore creative expression ✍️

📫 Let’s Connect

Popular repositories Loading

  1. vlsi-rtl-and-protocol-projects vlsi-rtl-and-protocol-projects Public

    Repository showcasing advanced RTL Design and Verification projects in Verilog and SystemVerilog — featuring complete implementations of UART, SPI, I2C, AHB, and AXI-Lite protocols with verificatio…

    1

  2. spunkycurative spunkycurative Public

    Config files for my GitHub profile.

  3. Verilog-designs Verilog-designs Public

    This repository contains Verilog HDL projects implementing combinational and sequential circuits including multiplexers, encoders, flip-flops, shift registers, counters, and memory modules. Ideal f…

    Verilog

  4. spi-master-slave-rtl-verification spi-master-slave-rtl-verification Public

    SPI Master–Slave RTL design and SystemVerilog verification project. Implements Mode-0 timing, shift-register based 12-bit data transfer, CS control, and clock-synchronized shifting. Includes a comp…

    SystemVerilog

  5. uart-design-verification uart-design-verification Public

    Parameterized UART Transmitter and Receiver in Verilog with odd parity support, verified using a SystemVerilog class-based testbench with generator, driver, monitor, scoreboard, and mailbox-based s…

    SystemVerilog

  6. I2C-master-slave I2C-master-slave Public

    Synthesizable I2C Master RTL with FSM-based control, START/STOP generation, ACK/NACK handling, and SDA bidirectional control. Includes SystemVerilog transaction-based verification environment with …

    Verilog