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1. ic-digital-1-ALU_chip ic-digital-1-ALU_chip Public

   A practice project implementing a modular UART-based ALU IC in Verilog, featuring a Master FSM, serial communication, and 8 distinct operations with testbench verification.

   Verilog

2. ic-digital-2-Convolution_Pooling_Coprocessor ic-digital-2-Convolution_Pooling_Coprocessor Public

   This is my practise project. A Verilog-based hardware accelerator for AI image processing, implementing 3x3 Convolution, ReLU, and 2x2 Max Pooling using FSMs.

   Verilog

3. project_RISC_V_v1 project_RISC_V_v1 Public

   This is version 1 of a 32-bit single-cycle RISC-V processor implemented in Verilog. Designed for Xilinx Vivado, it features a custom datapath and control unit supporting core I/R/B-type instruction…

   Verilog