Circuits and Systems Lab (CASlab)

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UPSET
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UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. D…
fault-tolerance electronic-design-automation static-timing-analysis
fault-tolerance electronic-design-automation static-timing-analysis fault-analysis single-event-transient
Verilog
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MIT License
•1•10•0•1•Updated Feb 19, 2026Feb 19, 2026

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