[Not ready] MSCCLPP EP implementation - #852
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Port DeepEP's high-throughput MoE dispatch/combine kernels onto MSCCL++
as an optional build target `mscclpp_ep_cpp`, gated by -DMSCCLPP_BUILD_EXT_EP
(OFF by default). Sources are lifted from DeepEP branch
`chhwang/dev-atomic-add-cleanup` and rebased onto upstream MSCCL++ APIs;
the NVSHMEM / IBGDA dependencies are replaced with `PortChannel` +
`MemoryChannel` + the new `Connection::atomicAdd` primitive.
Scope
-----
Intranode (NVLink-only):
* `Buffer` ctor/dtor: cudaMalloc nvl workspace, export IPC handle,
allocate FIFO + peer-pointer tables, start `ProxyService`.
* `sync()`: import peer IPC handles, upload peer pointer table,
build `MemoryDevice2DeviceSemaphore` + `MemoryChannel` per peer.
* `get_dispatch_layout`, `intranode_dispatch`, `intranode_combine`
ported verbatim (torch::Tensor ABI preserved).
Internode HT (NVLink + RDMA):
* `sync()` RDMA branch: cudaMalloc RDMA buffer + `bootstrap->barrier()`
(replacing NVSHMEM symmetric-heap allocation); register with
`all_transport`, exchange via `sendMemory`/`recvMemory`, build 12 IB
QPs/peer + 16 semaphores/peer + 16 port channels/peer.
* Full `internode.cu` port (notify_dispatch / dispatch / cached_notify
/ combine / get_dispatch_layout). The 4 raw `ChannelTrigger` atomic
sites are rewritten to call the new
`PortChannelDeviceHandle::atomicAdd(offset, value)` API; the single
`nvshmem_fence()` is replaced with `__threadfence_system()` (remote
visibility guaranteed by the subsequent port-channel barrier).
* `internode_dispatch` / `internode_combine` host code ported, with
the torch tensor marshalling and CPU spin-wait on mapped counters.
Low-latency (pure RDMA):
* Not ported. `low_latency_dispatch`, `low_latency_combine`,
`clean_low_latency_buffer`, `get_next_low_latency_combine_buffer`
throw `std::runtime_error`; the Python frontend refuses to
construct a Buffer with `low_latency_mode=True`.
Python layer
------------
* New pybind11 + libtorch Python extension `mscclpp_ep_cpp` (separate
from the nanobind `_mscclpp` because the EP ABI carries
`torch::Tensor` / `at::cuda::CUDAStream`).
* `mscclpp.ext.ep.Buffer` mirrors `deep_ep.Buffer`; exchanges device
IDs, IPC handles and the bootstrap UniqueId over the user's
`torch.distributed` process group before calling `sync()`.
* `mscclpp.ext` auto-imports `ep` if the extension is built.
Build
-----
* `src/ext/ep/CMakeLists.txt`: finds Python + Torch; warns and skips if
`CMAKE_PREFIX_PATH` doesn't point at `torch.utils.cmake_prefix_path`.
Falls back to Torch's bundled pybind11 if a standalone pybind11 is not
installed. Links `libtorch_python` explicitly (without it, `import
mscclpp_ep_cpp` fails with `undefined symbol: THPDtypeType`).
* Top-level `CMakeLists.txt` exposes the `MSCCLPP_BUILD_EXT_EP` option
(default OFF).
Tests
-----
* `test/python/ext/ep/test_ep_smoke.py`: skipped if the extension isn't
built. Covers Config round-trip, low-latency size hint, and the LL
construction guard. Multi-rank functional tests still to do on H100.
Notes
-----
* Builds against the preceding "atomic add" commit which adds
`Connection::atomicAdd` and `PortChannelDeviceHandle::atomicAdd` to
upstream MSCCL++.
* Intranode path verified end-to-end (build + import + smoke tests).
* Internode HT is code-complete but requires real IB hardware to
validate; see `src/ext/ep/README.md` for the detailed port plan and
remaining LL migration.
Port DeepEP's pure-RDMA low-latency (LL) MoE kernels from
csrc/kernels/internode_ll.cu (branch chhwang/dev-atomic-add-cleanup)
into the MSCCL++ EP extension. NVSHMEM / IBGDA device primitives are
replaced with MSCCL++ PortChannelDeviceHandle operations:
nvshmemx_barrier_all_block() -> port-channel signal+wait ring
nvshmemi_ibgda_put_nbi_warp(...) -> lane-0 PortChannel.put(...)
nvshmemi_ibgda_amo_nonfetch_add(...) -> lane-0 PortChannel.atomicAdd(...)
The atomicAdd path relies on the MSCCL++ Connection::atomicAdd /
PortChannelDeviceHandle::atomicAdd API cherry-picked from branch
chhwang/new-atomic-add; the LL dispatch path uses a signed delta
(-num_tokens_sent - 1) which the new int64_t signature supports.
Changes:
* New file src/ext/ep/kernels/internode_ll.cu (~530 lines) with the
three kernels clean_low_latency_buffer, dispatch<kUseFP8,...>,
combine<...> plus their launchers. rdma_buffer_ptr is threaded
through the launchers so the kernel can translate virtual addresses
into registered-memory offsets expected by MSCCL++.
* kernels/api.cuh: replace the single stub signature with full LL
launcher prototypes.
* buffer.cc: replace the four LL throw-stubs
(clean_low_latency_buffer, low_latency_dispatch,
low_latency_combine, get_next_low_latency_combine_buffer) with
torch-Tensor implementations ported from DeepEP/csrc/deep_ep.cpp.
* Drop src/ext/ep/internode_stub.cc and its CMake entry.
* python/mscclpp/ext/ep/buffer.py: remove the low_latency_mode=True
NotImplementedError guard; update docstring.
* test/python/ext/ep/test_ep_smoke.py: rename
test_low_latency_rejected -> test_low_latency_buffer_construct
to reflect that LL construction is now accepted.
* src/ext/ep/README.md: update status matrix, document the
NVSHMEM -> MSCCL++ translation table, and list the known
limitations.
This is a structural port: the kernels compile, link, and pass the
single-rank smoke tests, but end-to-end behaviour on multi-node H100
is not yet validated. Two known caveats:
1. Performance will NOT match IBGDA because MSCCL++ port channels
use a CPU proxy; this port is for functional parity, not latency.
2. Buffer::sync() in LL mode only connects peers that share the
same local GPU id (DeepEP convention), so the LL kernels assume
a one-GPU-per-node topology (num_ranks == num_rdma_ranks).
Multi-GPU-per-node LL layouts will need a follow-up in sync().
Tested:
cmake --build build -j --target mscclpp_ep_cpp # builds clean
pytest test/python/ext/ep/test_ep_smoke.py # 3 passed
Three issues blocked end-to-end intranode validation across multiple ranks. This commit fixes them and adds a 2/4/8-rank functional test. 1. Combine receiver: OOB __shared__ read In the combine receiver warp, the wait loop evaluated `channel_tail_idx[recv_lane_id] <= expected_head` before the `expected_head >= 0` guard. `channel_tail_idx` is a shared array of size `kNumRanks`, but the loop runs on all 32 lanes of a warp, so lanes with `recv_lane_id >= kNumRanks` indexed out of bounds. compute-sanitizer reported "Invalid __shared__ read of size 4 bytes" at combine<bf16,2,768>+0xdd0, surfaced asynchronously as cudaErrorIllegalAddress at the kernel launch site. Swap the operands so the rank-bounds check short-circuits the shared read. 2. Python bindings: UniqueId ABI `mscclpp::UniqueId` is a `std::array<uint8_t, N>` which pybind11 auto-converts to a Python `list`, silently overriding any `py::class_<UniqueId>` wrapper. Expose `create_unique_id` / `connect` as lambdas that produce/consume `py::bytes` and memcpy into a local `UniqueId`. Also coerce `bytes`->`bytearray` at the Python call site for `sync()` whose signature expects `pybind11::bytearray`. 3. Python frontend: communicator required for NVL-only sync `Buffer::sync()` uses `communicator->connect(ipc_config, ...)` on the pure-NVLink path, so the communicator must be initialized even when `num_rdma_ranks == 1` and `low_latency_mode == False`. Always broadcast the unique id and call `runtime.connect()` before `sync()`. Validation on a single H100x8 node via torchrun: - 2 ranks: dispatch 195 tokens, combine diff=0 - 4 ranks: dispatch 371 tokens, combine diff=0 - 8 ranks: dispatch 456 tokens, combine diff=0 Test harness added at test/python/ext/ep/test_intranode_multirank.py.
The `internode` kernels index device-side port channel handles as
`port_channel_handles[channel_id * num_ranks + peer_rank]`, where
`peer_rank` is a global rank in [0, num_ranks). `Buffer::sync` was
building that table by iterating `std::unordered_map<int, MemoryId>`
(and similarly for connections/semaphores), which yields hash order
rather than ascending rank order. Once the cross-node fan-out grew
beyond a single peer, a local rank's trigger for peer `r` landed on
the semaphore/memory pair of a different peer, so RDMA puts and
atomic tail updates went to the wrong destination and the forwarder
spun on a tail counter that never advanced.
Changes:
- Build `sema_ids` and `port_channel_handles` by iterating
`for (int r = 0; r < num_ranks; ++r)` and looking up the
connection / memory id for rank `r`, skipping ranks excluded by
low-latency mode (inserting a placeholder handle so the stride
stays `num_ranks`).
- Tag the RDMA-phase `sendMemory`/`recvMemory`/`connect` calls with
`kRdmaTag = 1` so they do not collide with NVL-phase tag-0
traffic between the same pair of ranks.
- Drop an unused `r` local in the NVL setup loop.
With this fix and a matched `libmscclpp.so` on both nodes, the
2-node x 8-GPU internode HT dispatch path completes successfully
(`[dispatch] OK`). Combine is still under investigation.
Also adds `test/python/ext/ep/test_internode_multirank.py`, a
torchrun-based 2-node functional test that exercises
`get_dispatch_layout` -> `internode_dispatch` -> `internode_combine`
and validates per-source-rank token values end-to-end.
Two issues prevented internode HT combine from completing on 2x8 H100: 1. Wrong prefix matrices passed to internode_combine. Combine runs in the reverse direction of dispatch, so it must consume the receiver-side matrices returned by dispatch (recv_rdma_channel_prefix_matrix, recv_rdma_rank_prefix_sum, recv_gbl_channel_prefix_matrix), not the sender-side rdma_channel_prefix_matrix / gbl_channel_prefix_matrix. This matches DeepEP's deep_ep/buffer.py::internode_combine handle unpacking. Without the fix the NVL forwarder's 'NVL check' timed out because token_start_idx/token_end_idx were computed against the wrong per-channel layout. 2. Cross-rank race between dispatch and combine. Even with the correct matrices, launching combine immediately after dispatch deadlocked the forwarder NVL check (tail stuck one short of expected_head) because peers still had in-flight dispatch proxy traffic while fast ranks had already started combine. A torch.cuda.synchronize() + dist.barrier() between the two calls makes the test pass deterministically on 16 ranks (combine diff == 0, max|expected| up to 60.0). The barrier in the test is a workaround; the real fix belongs in Buffer::internode_dispatch / Buffer::internode_combine so the dispatch->combine handoff fully fences outstanding proxy work across ranks. Marked with an XXX comment in the test.
Refresh status docs and comments now that internode HT dispatch and combine have been validated end-to-end on 2 nodes x 8 H100 GPUs via test/python/ext/ep/test_internode_multirank.py (all 16 ranks recover their per-rank token payloads with zero diff). - src/ext/ep/README.md: consolidate the previously duplicated README into a single document; mark intranode and internode HT dispatch and combine as validated in the status table; add a 'Running the tests' section with torchrun examples for both the intranode and the 2x8 internode setups; record the dispatch->combine torch.cuda.synchronize() + dist.barrier() requirement under Known limitations; mark Phase 2 DONE and keep Phase 3 (LL) as structural port, untested. - python/mscclpp/ext/ep/buffer.py: update the module docstring and the Buffer constructor docstring to say internode HT is validated and clarify that LL mode is untested on multi-node hardware. - src/ext/ep/buffer.cc: drop the stale 'NVSHMEM support not yet ported' and 'low-latency paths still stubbed' comments. mscclpp_ep does not use NVSHMEM at all (PortChannel/MemoryChannel replace it), and the LL paths are a structural port that is present but untested, not stubbed. Note validation on 2x H100x8 in the internode section header.
- Buffer::sync no longer drops non-same-GPU-id peers in low_latency_mode. DeepEP's original filter was safe because its LL path used NVSHMEM; this port drives LL via PortChannel so the kernel indexes port_channel_handles[local_expert*num_ranks + dst_rank] for every dst_rank. All peers now get a real memory/connection/semaphore/port channel entry. - Add test/python/ext/ep/test_low_latency_multirank.py (LL dispatch+combine functional round-trip, BF16 only). Works cross-node in DeepEP's 1-GPU-per-node topology. - Known limitation documented in src/ext/ep/README.md and the test docstring: intra-node 8-GPU LL currently hangs because every peer transfer routes through the CPU proxy over IB loopback between distinct HCAs on the same host, and (separately) CudaIpcConnection::atomicAdd is a 64-bit op which mis-aligns the 32-bit rdma_recv_count slots when used for same-node peers. Proper fix needs a mixed-transport LL variant (MemoryChannel for same-node, PortChannel for cross-node) or 64-bit counters.
Gated behind MSCCLPP_EP_BENCH=1 to keep correctness runs fast. Reports per-iter latency (max across ranks, CUDA-event timed) and aggregate effective bandwidth (sum across ranks, dispatch+combine payload bytes). Tunable via MSCCLPP_EP_BENCH_WARMUP / _ITERS / _TOKENS / _HIDDEN. Bench reuses the Buffer allocated for the correctness phase and self-skips if the requested hidden exceeds the per-peer NVL/RDMA budget.
Previously the optional benchmark measured full round-trip latency. Split it to time dispatch alone (N iters) and combine alone (N iters reusing one dispatch output), reporting per-phase latency (max across ranks) and aggregate effective bandwidth (sum across ranks). Applies to intranode HT, internode HT, and the (currently unreachable on intra-node 8-GPU) LL test. Internode HT keeps the sync+barrier guard between dispatch and combine but excludes it from either phase's timing.
…o int64 The low-latency dispatch/combine kernels signal recv counts via MSCCL++ PortChannel.atomicAdd, which lowers to IB IBV_WR_ATOMIC_FETCH_AND_ADD. That opcode requires the remote address to be 8-byte aligned, but LowLatencyLayout packed the per-expert signaling slots as int32. Odd slots landed at offset %8 == 4; the NIC silently dropped those atomics and the target rank spun forever in recv_hook (observed: even->odd direction works, odd->even does not, across all tested topologies including 2-rank intra-node, 8-rank intra-node, and 2-node 1-GPU-each). Widen dispatch_rdma_recv_count_buffer / combine_rdma_recv_flag_buffer to int64_t, update clean kernel + kernel signatures + next_clean pointers accordingly, and add int64_t overloads for st_na_release / ld_acquire_sys_global in utils.cuh. Also drop the bogus self CUDA-IPC connection in Buffer::sync() that was previously skewing the cross-rank buildAndAddSemaphore handshake order; the kernel's same-rank branch uses a direct warp copy and never touches the self port-channel slot (filled with a zero-initialized placeholder so the [local_expert*num_ranks + dst_rank] indexing still holds).
Dropping the self ipc_cfg connection caused cudaErrorInvalidResourceHandle on multi-node launches. Keep the self connection (needed by other code paths that assume every rank is in the connections map) but continue to skip the self slot in the semaphore + port-channel construction loops so the kernel's [local_expert*num_ranks + dst_rank] indexing hits only peer handles; the self slot is a zero-initialized placeholder since the kernel's same-rank branch uses a direct warp copy.
The prior commit skipped r==rank in the semaphore and port-channel build loops on the theory that the self-slot handshake skew was the cause of LL direction asymmetry. That was wrong (the real bug was int32 atomic alignment), and skipping self breaks other code paths that assume every rank slot is represented -- cross-node HT and LL failed with cudaErrorInvalidResourceHandle at the first barrier after Buffer init. Restore the self-inclusive loop.
When all ranks live on the same host (num_rdma_ranks == 1), the LL
kernels now bypass PortChannel/IB-loopback entirely. In Buffer::sync()
we additionally:
- allGather IPC handles for each rank's rdma_buffer_ptr and
cudaIpcOpenMemHandle them into peer_rdma_bases[]
- build per-peer MemoryChannels over CUDA IPC connections (tag=2)
used only for the LL barrier ring
The three LL kernels (clean / dispatch / combine) gain a kIpcPath
template parameter and two extra args (peer_rdma_bases,
memory_channel_handles). At each peer op:
- put -> peer-mapped warp copy over NVLink
- atomicAdd-like flag store -> single-writer st_na_release on peer ptr
- signal/wait barrier -> MemoryChannel signal/wait
Cross-node LL (num_rdma_ranks > 1) is untouched; the IPC setup block is
a no-op. The host launch wrappers select the variant via use_ipc_path.
Each local expert sends one copy per dispatched token back to its owner, so the bytes actually on the wire during combine match dispatch. The previous num_tokens×hidden under-counted by ~num_topk×, making combine BW look artificially low next to dispatch.
- Report both per-rank and aggregate BW to align with NCCL-EP's ep_bench (which reports per-rank GB/s). - Accept MSCCLPP_EP_LL_TOKENS/HIDDEN/TOPK/EXPERTS_PER_RANK env overrides so we can match external benchmark problem sizes (NCCL-EP LL defaults are num_tokens=128, hidden=7168, top_k=8).
Same alignment with NCCL-EP ep_bench as the LL test: report both per-rank (agg/num_ranks) and aggregate throughput.
LL dispatch/combine are latency-bound at typical problem sizes: for num_experts=32 the previous grid was cell_div(32,3)=11 blocks, i.e. 8% of a 132-SM H100. The recv-side bodies already stride tokens by sm_id, so extra blocks parallelize token work linearly. Extra blocks past num_experts are gated out of the send/count phases by the existing 'responsible_expert_idx < num_experts' check. Cap at the device's SM count (cooperative launch + launch_bounds(960,1) allow one block per SM).
On the PortChannel (cross-node) path the extra blocks don't help: the dispatch recv loop strides tokens per-warp-group (not per-SM), and the additional blocks instead add cooperative-grid sync overhead and increase concurrent host-proxy FIFO traffic. Measured cross-node dispatch regressed from 1013us to 3063us when the unconditional grid bump was active. Keep the scaled grid for the IPC path (intra-node), where combine-recv and dispatch token striding scale with sm_id and the 1.2-1.3x speedup reproduces.
The LL combine benchmark was cloning the ~58 MB dispatch recv buffer
('recv_x.clone()') on every timed iteration, adding ~20 us of D2D
memcpy per sample and masking kernel-level changes. It also called
torch.empty() for the output inside the loop. Both now live outside
the timed region; the kernel is invoked against a persistent bench_out
and the recv_x produced by the most recent dispatch.
NCCL-EP's LL dispatch/combine kernel uses (numWarpGroups=1,
numWarpsPerGroup=32) when num_experts <= device_num_sms, giving each
SM ownership of a single expert and 32 warps to cooperate on its
recv-side per-(expert, src_rank) work. We were using (3, 10) — 3
experts per SM, 10 warps per (expert, rank) pair — which left a
significant amount of recv-side parallelism on the table because each
warp had to walk ~3x more tokens sequentially.
Switching to (1, 32) for both dispatch and combine matches NCCL-EP's
structure for typical EP sizes (num_experts in {32, 64, 256}) where
num_experts <= 132 SMs.
The static_assert kNumMaxTopK + 1 <= kNumWarpGroups * kNumWarpsPerGroup
still holds (9 <= 32) and the wider block also lets the staging loop
process the hidden-dim with one int4 per thread (hidden_bf16_int4=896
fits easily in 992 working threads).
Cross-node LL regressed when (1, 32) was applied uniformly: dispatch 1031us -> 1570us, combine 2553us -> 3484us. Larger grid means more concurrent putWithSignal calls onto the host-proxy FIFO and a costlier cg::this_grid().sync() between phases, both of which dominate the IB path even though more SMs help the recv-side compute. Make (kNumWarpGroups, kNumWarpsPerGroup) path-dependent: (1, 32) when use_ipc_path, (3, 10) otherwise. Restores cross-node performance and keeps the intra-node win.
- Add MSCCLPP_EP_BENCH_EXPERTS / _TOPK env knobs so the bench phase can match NCCL-EP's `ep_bench -a ht` defaults (256 experts, top-8). The functional check above continues to use the smaller (num_ranks*4 experts, topk=4) configuration. - Switch BW accounting from recv_tokens*hidden to bench_tokens*hidden, matching NCCL-EP's `RDMA_send` per-rank byte count. The previous formula counted DeepEP's expanded recv layout (one row per (token,src_rank) pair), inflating reported GB/s ~5x and making cross-stack comparisons misleading.
Same change as the intra-node bench (commit 4ed6f22), applied to the cross-node test: - Add MSCCLPP_EP_BENCH_EXPERTS / _TOPK env knobs so the bench phase can match NCCL-EP's `ep_bench -a ht` defaults (256 experts, top-8). - Switch BW accounting from recv_tokens*hidden to bench_tokens*hidden, matching NCCL-EP's `RDMA_send` per-rank byte count.
Each mscclpp::ProxyService spawns one host-side proxy thread that drains its FIFO and posts IB work requests. With LL combine pushing ~1k put + 60 atomicAdd FIFO entries per iter, that single thread is the wall-clock bottleneck on cross-node runs. Split the channel set across kNumProxyServices=4 separate services so the host-side dispatch parallelism scales linearly. SemaphoreIds and MemoryIds are scoped to a ProxyService, so: - addMemory() is broadcast to every service in the same global order so a single MemoryId still identifies the memory everywhere. - Each (peer_rank, channel_idx) is assigned to one proxy_idx via round-robin; the resulting PortChannel is built on that proxy and inherits its FIFO. The kernel is unchanged: the flat handle array routes the right way automatically. No kernel-level changes, no tuning of QP count, no new env knobs.
… 1 on Blackwell) Override at runtime with MSCCLPP_EP_NUM_PROXIES. N=8 is the knee on H100+IB; N>=12 collapses from CPU oversubscription. Intra-node LL is unchanged.
Add dist.barrier() + dist.destroy_process_group() in a finally block so non-zero ranks don't poll the TCPStore after rank 0 (the store server) exits, which produced noisy 'recvValue failed / Connection was likely closed' stack traces from ProcessGroupNCCL's HeartbeatMonitor. Also pass device_id to init_process_group in the internode test to silence 'Guessing device ID based on global rank' warnings.
Aligns with NCCL-EP's ep_bench convention (BW computed from average time across ranks). Previously we reported only the max time and computed BW per-rank, which made our numbers more pessimistic than NCCL-EP's.
Clarify the EP backend phases and reduce duplicated low-level machinery: - use MSCCL++ memory-channel semaphores for HT device barriers - rename HT routing-count/exchange launchers and document each phase - size LL workspace exactly instead of reserving a fixed 32 MiB - replace blanket cooperative-launch macros with scoped launch configs - remove unused PTX helpers and the obsolete EP constants header - make EP default-on for supported CUDA/Python builds and detect concrete native GPU architectures Also remove invalid EP install-extra docs, a non-importable GPUBufferPool standalone test, and the orphan tma_pipeline_perf CMake target. Restore Unix socket lifecycle code to origin/main and fix torch subgroup bootstrap source handling. Validated with 32-GPU LL rank-major and 16-GPU HT benchmarks, plus 2/4-GPU HT and LL BF16/FP8/direct-send correctness runs. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Apply the repository clang-format 18 style to the cooperative combine launch macro so tools/lint.sh passes for both C++ and Python. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Expose the sm_90+ bulk copy engine (cp.async.bulk / cp.reduce.async.bulk) as a pointer-based device API in a new header, mscclpp/bulk_device.hpp. The primitives are channel-free by design. Bulk copies move bytes between global and shared memory and do not care whether the global side is local or peer mapped; channels answer where a peer's memory is and how to synchronize with it. Those concerns compose through a plain pointer. The expert-parallel kernels that motivate this feature gather from arrays of raw peer pointers and use channels only for signal/wait, so binding the primitives to a channel would not serve them. This also matches how SwitchChannel exposes multimem: a public, pointer-based primitive is the foundation. Surface: BulkBarrier load completion, with caller-held phase parity bulkLoad global -> shared, tracked by a barrier bulkStore shared -> global bulkReduceStore<T,Op> shared -> global, accumulating at the destination bulkStoreCommit close the current bulk group bulkStoreWait<N> stores have landed bulkStoreWaitSource<N> source tiles are reusable, stores may be in flight bulkFence order generic shared accesses against the async proxy isBulkSupported() host capability query, alongside isNvlsSupported() Notes on specific choices: - MSCCLPP_BULK_AVAILABLE gates the declarations, so unguarded use on an unsupported target is a compile error rather than a silent no-op. This follows the existing __CUDA_ARCH__ >= 900 call-site guards used for NVLS. - BulkBarrier storage is declared on every target, including host compilation, because host code must size the dynamic shared memory that holds barriers. Only the operations are gated. - expect, arrive and arriveAndExpect are separate so a multi-source gather can accumulate N loads against one barrier and wait once. Every expect for a batch must precede the arrival that completes the arrival count; arriveAndExpect carrying the batch total is documented as the recommended form. - init() includes the proxy fence that publishes the barrier to the async proxy. relaxedInit() omits it so an array of barriers can be set up under one fence, mirroring signal() and relaxedSignal(). - wait() advances the phase, so a barrier is initialized once and reused rather than reinitialized per batch. - bulkStoreWait and bulkStoreWaitSource are distinct because a double-buffered store pipeline needs to refill a tile without draining the store. Tests. test/unit/bulk_tests.cu covers the primitives on a single GPU. The reduction tests seed the destination so they distinguish accumulate from overwrite. test/mp_unit/bulk_pattern_tests.cu adds BulkPatternTest, three multi-rank kernels shaped after expert-parallel dispatch and combine: a staged push, a multi-source pull and reduce that is double buffered across chunks, and the same reduction expressed as a push using bulkReduceStore. Verified on H200 (sm_90): unit_tests 40/40, mp_unit_tests 60/60 at 2 ranks, BulkPatternTest 3/3 at 6 ranks. Guard behavior confirmed: guarded code builds at sm_80 and for multi-arch sm_80+sm_90, unguarded code fails to compile at sm_80, and an unsupported reduction type fails its static_assert.
<cuda_bf16.h> was included only where MSCCLPP_BULK_AVAILABLE is 1, so __nv_bfloat16 could not be named in a host translation unit and bulkReduceStore<__nv_bfloat16> could not be instantiated from one. The unit test only compiled because gpu_utils.hpp happened to pull the type in. Gate the include on MSCCLPP_DEVICE_CUDA instead, matching switch_channel_device.hpp. Plain host builds without the CUDA toolkit are unaffected. Found while validating on GB200 (sm_100), where the header is used without that incidental include. Verified on GB200 (sm_100, CUDA 13.0, aarch64): 11/11 standalone checks including peer-memory load, store and reduce, and 4-GPU concurrent accumulate into one buffer over 50 iterations. Guard behavior holds under CUDA 13: guarded code builds at sm_80 and multi-arch sm_80+sm_100a, unguarded code fails to compile at sm_80, plain g++ reports sizeof(BulkBarrier)=8. Re-verified on H200 (sm_90): unit_tests 40/40, mp_unit_tests 60/60 at 2 ranks.
Three cleanups found by running things that had not been run. Doxygen strips everything guarded by MSCCLPP_BULK_AVAILABLE, because the macro derives from __CUDA_ARCH__ and doxygen does not define it. Every directive added to cpp_api.rst therefore failed: WARNING: doxygenfunction: Cannot find function "mscclpp::bulkLoad" in doxygen xml output for project "mscclpp" from directory: ./doxygen/xml Add MSCCLPP_BULK_AVAILABLE=1 to PREDEFINED in the Doxyfile, next to the existing MSCCLPP_DEVICE_COMPILE and MSCCLPP_DEVICE_CUDA entries that exist for the same reason. Sphinx now emits no bulk warnings and every symbol renders. Bind isBulkSupported() as is_bulk_supported and export it, matching is_nvls_supported. Replace the unit test's homegrown compute-capability check with isBulkSupported(). The mp_unit tests already used it; having two ways to ask the same question is what the host query exists to avoid. Also document that the cross-device atomicity of bulkReduceStore() is established by measurement rather than by the PTX documentation, so callers do not take it as guaranteed. Verified on H200: docs build clean of bulk warnings and all ten symbols present in the generated HTML; unit_tests 40/40; mp_unit_tests 60/60 at 2 ranks; Python bindings build and mscclpp.is_bulk_supported() returns True.
Where MSCCLPP_BULK_AVAILABLE is 0, BulkBarrier has no operations, only the storage declared so host code can size shared memory holding barriers. Clang then warns on every ROCm translation unit that includes the header: include/mscclpp/bulk_device.hpp:139:23: warning: private field 'mbar_' is not used [-Wunused-private-field] Mark the member maybe_unused. No effect where the operations exist. Verified on MI300X (ROCm 7.2, gfx942): warning count for this field 0, and both suites match the merge-base exactly -- unit_tests 32 ran / 23 passed / 9 skipped, mp_unit_tests --filter=-Ib 29 ran / 24 passed / 3 failed. The three failures are CommunicatorTest.BasicWrite, .WriteWithDeviceSemaphores and .WriteWithHostSemaphores, which fail identically on the merge-base; this node has no IB device. Re-verified on H200: unit_tests 40/40, mp_unit_tests 60/60.
Mark kernel parameters [[maybe_unused]] at their declarations instead of adding #else blocks with (void)param casts when bulk copy is unavailable. This keeps the unsupported-target path declarative and removes 25 lines of warning-only code. Verified with nvcc at sm_80, the H200 bulk tests (6/6 unit, 3/3 multi-rank), and the MI300X ROCm build (no unused-parameter warnings; unit tests 23 passed / 9 skipped).
…t converted to larger type' Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
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## Summary Adds pointer-based 1-D bulk-copy primitives for NVIDIA sm_90+ in `mscclpp/bulk_device.hpp`: - `BulkBarrier` for reusable async-load completion - `bulkLoad` and `bulkStore` for global ↔ shared copies - `bulkReduceStore<T>` for copy-engine reduction into global or peer memory - commit, completion-wait, source-reuse-wait, and proxy-fence helpers - `isBulkSupported()` / `is_bulk_supported` capability queries The API operates on global pointers, including peer-mapped pointers. It does not add `MemoryChannel` methods: EP kernels use raw peer-pointer arrays for data movement and channels only for synchronization. The API covers all TMA instructions used by #852 and `qinghuazhou/unified_ep_bench_ht_python`. Unsupported device targets fail at compile time instead of silently doing nothing. `BulkBarrier` storage remains host-visible so launch code can size dynamic shared memory. The store API separates destination completion from source-tile reuse for pipelined kernels. `bulkReduceStore` currently supports `Add` for `float`, `__nv_bfloat16`, and `uint32_t`; unsupported combinations fail a `static_assert`. ## Tests - Single-GPU tests: load, multi-source gather, barrier reuse, pipelined store, and reduction - Multi-rank EP-shaped tests: - staged dispatch to peer memory - double-buffered multi-source combine - push combine with remote reduction - Doxygen/Sphinx coverage for the new API - Python binding build and import | Platform | Result | |---|---| | H200, sm_90 | `unit_tests` 40/40; `mp_unit_tests` 60/60; patterns 3/3 at 6 ranks | | GB200, sm_100 | `unit_tests` 40/40; non-IB `mp_unit_tests` 32/32; patterns 3/3 at 4 ranks | | MI300X, ROCm | Results match the merge-base: 23 passed / 9 skipped; non-IB mp tests 24 passed / 3 pre-existing failures | ## Limitation Concurrent reduction from several GPUs into the same peer address produced exact results across repeated H200 and GB200 runs, but cross-peer atomicity was not found in the PTX documentation. The header documents this as empirical rather than guaranteed.
Resolve duplicate bulk-copy additions using the reviewed upstream implementation. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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## Summary Assign low-latency dispatch epochs once in `MoELowLatencyRuntime` and pass the epoch to dispatch and combine through `Workload`. Previously, each CUDA block derived the epoch from device workspace state while block 0 updated that state without a grid-wide ordering guarantee. Late blocks could therefore observe a different epoch and wait indefinitely on readiness flags. ## Changes - Add a host-owned dispatch epoch counter to `MoELowLatencyRuntime`. - Increment the epoch once before each dispatch. - Pass the same epoch to dispatch and its subsequent combine operation. - Use the workload epoch for rank-major synchronization. - Remove device-side epoch generation, publication, and workspace storage. This gives every block in a launch one immutable epoch value. ## Validation - Passed eager rank-major tests at capacities 1 and 2. - Passed eager expert-major tests at capacity 2. - Passed bit-exact 2-rank and 4-rank multi-operation CUDA Graph replays. - Passed all 10 SGLang dispatcher tests. - Completed six 32-rank serving rounds with 40/40 responses and no scheduler watchdog timeouts.
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