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db
db
 
 
incremental_db
incremental_db
 
 
output_files
output_files
 
 
work
work
 
 
AdderE.v
AdderE.v
 
 
AdderF.v
AdderF.v
 
 
Control_unitD.v
Control_unitD.v
 
 
Decode.v
Decode.v
 
 
Execute.v
Execute.v
 
 
Fetch.v
Fetch.v
 
 
Hazardmux.v
Hazardmux.v
 
 
Hazardunit.v
Hazardunit.v
 
 
Memory.v
Memory.v
 
 
PC.v
PC.v
 
 
PCmuxF.v
PCmuxF.v
 
 
RegisterfileD.v
RegisterfileD.v
 
 
Schematic.png
Schematic.png
 
 
alu.v
alu.v
 
 
alumux.v
alumux.v
 
 
datamem.v
datamem.v
 
 
instmemF.v
instmemF.v
 
 
pipeline_riskv.cr.mti
pipeline_riskv.cr.mti
 
 
pipeline_riskv.mpf
pipeline_riskv.mpf
 
 
schematic2.png
schematic2.png
 
 
signextD.v
signextD.v
 
 
toppipeline.qpf
toppipeline.qpf
 
 
toppipeline.qsf
toppipeline.qsf
 
 
toppipeline.qws
toppipeline.qws
 
 
toppipeline.v
toppipeline.v
 
 
vsim.wlf
vsim.wlf
 
 
writeback.v
writeback.v
 
 

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A 5 stages pipelined risk-v based processor implemented with verilog along with the implementation of a hazard handling unit. The design elaboration was doe using Quartus Prime tool to produce the schematic.

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