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khenderson20/README.md

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๐Ÿ›ฐ๏ธ About Me

  • ๐Ÿ”ญ Currently building clearCore a transparent, educational MIPS CPU simulator with a 5-stage pipeline, hazard detection, data forwarding, and a hand-rolled terminal UI datapath visualizer built on FTXUI
  • ๐Ÿ“ Deep into computer architecture, digital logic, and low-level systems programming
  • ๐Ÿ–ฅ๏ธ Daily driver: Fedora 44 with KDE Plasma, CLion as my IDE of choice
  • ๐ŸŽน Synth enthusiast, JUCE and VCV Rack show up in my toolbox for a reason
  • ๐ŸŒฑ Fresh Graduate from my local Computer Science program at University of Texas at San Antonio
  • ๐Ÿ’ฌ "Ever tried. Ever failed. No matter. Try again. Fail again. Fail better."

๐Ÿš€ Technical Expertise

Category Technologies
Languages Python C C++ Java JavaScript TypeScript Zig SQL Bash
Systems & Low-Level CMake GCC Make Linux
Web & Frameworks React Next.js FastAPI Node.js Tailwind
Cloud & DevOps AWS Docker Git GitHub Actions
AI & Data IBM Watsonx Pandas LangChain
Creative Tech JUCE VCV Rack
Tools & Editors CLion VS Code Vim

๐Ÿง  Featured Projects

clearCore sonic-forge-dsp

kevin-portfolio dotfiles


๐Ÿ“Š GitHub Stats

GitHub Streak

"Ever tried. Ever failed. No matter. Try again. Fail again. Fail better."

Pinned Loading

  1. clearCore clearCore Public

    Transparent, educational 5-stage pipeline CPU simulator: hazard detection, data forwarding, and a real-time TUI/Qt6 GUI that shows every stall and flush. MIPS means "without interlocked pipeline stโ€ฆ

    C++ 11 1