Fizz Buzz in Verilog

Hardware solver for Fizz Buzz.

Uses fast divisibility test described in D. Lemire, O. Kaser, and N. Kurz, Faster Remainder by Direct Computation,2018.

Ports

input  logic [7:0] number
output logic       fizz
output logic       buzz

Requirements

• IceStorm
• nextpnr-ice40
• SymbiYosys (required for formal verification)
• Icarus Verilog (required for simulation)

Build instructions

Synthesize for IceBreaker board:
$ make

Run formal verification (requires SymbiYosys):
$ make formal

Run simulation (requires Icarus Verilog):
$ make test

Generate timing report:
$ make timing

Generate parameters for fast divisibility test:
$ python scripts/generate_div_params.py

Supported hardware

• IceBreaker board