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Add parallel functional RTL simulation for MLO #1644

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Add parallel functional RTL simulation for MLO #1644

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ffde95d
Add parallel functional RTL SIM for MLO
klassen9 Jul 27, 2026
4dbc138
Merge remote-tracking branch 'finn/dev' into feature/parallel_mlo_rtlsim
klassen9 Jul 30, 2026
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4 changes: 4 additions & 0 deletions src/finn/builder/build_dataflow_config.py
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Original file line number Diff line number Diff line change
Expand Up @@ -384,6 +384,10 @@ class DataflowBuildConfig:
#: loop_body_hierarchy and loop_body_range
mlo: Optional[bool] = False

#: If set to True, MLO stitched-IP rtlsim verification uses the parallel
#: "stream tap + body" path that simulates all loop iterations concurrently
mlo_parallel_rtlsim: Optional[bool] = False

#: A List of strings that specify the PyTorch metadata hierarchy to
#: be used for the loop body hierarchy. Each item in the list should
#: be a string that represents a level in the hierarchy.
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11 changes: 9 additions & 2 deletions src/finn/builder/build_dataflow_steps.py
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Expand Up @@ -161,7 +161,11 @@
extract_model_config_to_json,
)
from finn.util.fpgadataflow import is_mlo, warn_hls_rtl_dsp_conflict
from finn.util.rtlsim import annotate_rtlsim_performance, mlo_prehook_func_factory
from finn.util.rtlsim import (
annotate_rtlsim_performance,
mlo_prehook_func_factory,
run_parallel_mlo_rtlsim,
)
from finn.util.test import execute_parent
from finn.util.vivado import parse_ooc_synth_results

Expand Down Expand Up @@ -1182,7 +1186,10 @@ def step_create_stitched_ip(model: ModelWrapper, cfg: DataflowBuildConfig):
if cfg.verify_rtlsim_behavioral:
verify_model.set_metadata_prop("rtlsim_behavioral", "1")
if is_mlo(model):
verify_mlo(verify_model, cfg, "stitched_ip_rtlsim")
if cfg.mlo_parallel_rtlsim:
run_parallel_mlo_rtlsim(verify_model, cfg)
else:
verify_mlo(verify_model, cfg, "stitched_ip_rtlsim")
for loop_node in verify_model.get_nodes_by_op_type("FINNLoop"):
snapshot_fifo_logs(cfg, "stitched_ip_rtlsim", loop_context=loop_node.name)
snapshot_fifo_logs(cfg, "stitched_ip_rtlsim")
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