Skip to content
BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

4 Commits
doc
doc
 
 
quartus
quartus
 
 
src
src
 
 
.gitignore
.gitignore
 
 
AGENTS.md
AGENTS.md
 
 
LICENSE
LICENSE
 
 
README.md
README.md
 
 

Repository files navigation

FPGA Elevator Controller

English | 中文

VHDL-93 Quartus II Cyclone III EP3C40Q240C8 9 Modules 1881 Lines MIT License

A 3-floor elevator controller implemented in VHDL-93 with a top-down hierarchical design, synthesized and verified with Quartus II 9.1, and deployed on a Cyclone III EP3C40Q240C8 development board.

English

Overview

This project implements a 3-floor elevator controller on FPGA using EDA techniques. It follows a top-down hierarchical design methodology in VHDL-93, covering synthesis, functional simulation, and on-board deployment. The controller is built around a 10-state main FSM running the SCAN (elevator) scheduling algorithm, with independent door control, request handling, and output driving sub-modules.

This is a course design project for EDA technology education.

Features

Category Feature Description
Core 3-Floor Movement Up/down movement with directional constraints (no down-call on floor 1, no up-call on floor 3)
Core Door Control 10-second auto open/close with manual open/close button override
Core Floor Display Real-time 7-segment display of current floor
Core Idle Return Automatic return to floor 1 when no requests remain
Innovation Alarm System Toggle alarm with LED blink and buzzer tone
Innovation Arrival Buzzer 0.5s beep notification on floor arrival
Innovation Direction LEDs Up/Down direction indicator lights

Tech Stack

 Language     VHDL-93 (IEEE STD_LOGIC_1164, STD_LOGIC_UNSIGNED)
 EDA Tool     Quartus II 9.1 (32-Bit)
 Device       Cyclone III EP3C40Q240C8 (240-pin PQFP)
 Board        Kang Xin GW48 series (GW3C40 adapter, Mode NO.5)
 Design       Top-down hierarchical, dual-process FSM
 Reset        Asynchronous active-low (rst_n)
 I/O          12 inputs + 12 outputs = 24 pins

Architecture

graph TD
    subgraph TOP["elevator_top — Top-Level Entity"]
        direction TB

        CLK["clk_divider<br/><sub>50MHz &rarr; 1Hz / 100Hz / 500Hz / 1kHz</sub>"]

        subgraph INPUT["Input Processing"]
            DEB["debounce &times;10<br/><sub>2-stage sync + counter + edge detect</sub>"]
            REQ["request_handler<br/><sub>3&times;3-bit register bank, SCAN support</sub>"]
        end

        subgraph CONTROL["Control Logic"]
            FSM["elevator_ctrl<br/><sub>10-state SCAN FSM</sub>"]
            DOOR["door_controller<br/><sub>4-state door FSM, 10s timer</sub>"]
        end

        subgraph OUTPUT["Output Drivers"]
            DISP["display_driver<br/><sub>7-segment decoder</sub>"]
            ALM["alarm_controller<br/><sub>Toggle alarm + LED blink</sub>"]
            BUZ["buzzer_driver<br/><sub>Arrival beep + alarm tone</sub>"]
        end
    end

    CLK --> DEB
    DEB --> REQ
    REQ -- "req_up/dn/go<br/>any_request" --> FSM
    FSM -- "clear_req" --> REQ
    FSM -- "open/close cmd" --> DOOR
    DOOR -- "door_opened<br/>door_closed" --> FSM
    FSM -- "current_floor" --> DISP
    ALM -- "alarm_active" --> FSM
    ALM -- "buzzer_en" --> BUZ

    style TOP fill:#E3F2FD,stroke:#1565C0,stroke-width:2px,color:#0D47A1
    style INPUT fill:#E8F5E9,stroke:#2E7D32,stroke-width:1px
    style CONTROL fill:#FFF3E0,stroke:#E65100,stroke-width:1px
    style OUTPUT fill:#F3E5F5,stroke:#6A1B9A,stroke-width:1px
    style CLK fill:#BBDEFB,stroke:#1565C0
    style DEB fill:#C8E6C9,stroke:#2E7D32
    style REQ fill:#C8E6C9,stroke:#2E7D32
    style FSM fill:#FFE0B2,stroke:#E65100
    style DOOR fill:#FFE0B2,stroke:#E65100
    style DISP fill:#E1BEE7,stroke:#6A1B9A
    style ALM fill:#E1BEE7,stroke:#6A1B9A
    style BUZ fill:#E1BEE7,stroke:#6A1B9A
Loading

Module Index

Module File Lines Clock Description
elevator_top elevator_top.vhd 617 All Top-level integration and component instantiation
clk_divider clk_divider.vhd 132 50MHz Clock divider: 1Hz, 100Hz, 500Hz, 1kHz outputs
debounce debounce.vhd 99 100Hz Generic button debounce with edge detection
request_handler request_handler.vhd 156 100Hz Request register with clear-priority-over-set
elevator_ctrl elevator_ctrl.vhd 433 1Hz Main 10-state FSM with SCAN scheduling
door_controller door_controller.vhd 196 1Hz 4-state door FSM with 10s auto-close timer
display_driver display_driver.vhd 66 — Pure combinational 7-segment decoder
alarm_controller alarm_controller.vhd 88 100Hz+1Hz Toggle alarm with LED blink (0.5Hz)
buzzer_driver buzzer_driver.vhd 94 500Hz Dual-mode buzzer: arrival beep + alarm tone

State Machine

The main controller (elevator_ctrl) implements a 10-state FSM with the SCAN (elevator) scheduling algorithm:

stateDiagram-v2
    [*] --> S_IDLE

    S_IDLE --> S_CHECK_REQ : any_request = 1
    S_IDLE --> S_RETURN_HOME : idle timeout<br/>&amp; floor != 1F

    S_CHECK_REQ --> S_DOOR_OPENING : need_stop = 1
    S_CHECK_REQ --> S_MOVING_UP : req_above &amp; dir = UP
    S_CHECK_REQ --> S_MOVING_DOWN : req_below &amp; dir = DOWN

    S_MOVING_UP --> S_ARRIVED : floor + 1
    S_MOVING_DOWN --> S_ARRIVED : floor - 1

    S_ARRIVED --> S_DOOR_OPENING : need_stop = 1
    S_ARRIVED --> S_MOVING_UP : continue up
    S_ARRIVED --> S_MOVING_DOWN : continue down

    S_DOOR_OPENING --> S_DOOR_OPEN : immediate
    S_DOOR_OPEN --> S_DOOR_CLOSING : door_closed
    S_DOOR_CLOSING --> S_CHECK_REQ : complete

    S_RETURN_HOME --> S_MOVING_DOWN : floor &gt; 1F
    S_RETURN_HOME --> S_IDLE : at 1F or new request

    S_ALARM --> S_IDLE : alarm_active = 0

    note right of S_ALARM
        Highest priority.
        Any state transitions
        here when alarm is active.
    end note
Loading
Code State Description
0000 S_IDLE Idle at current floor, waiting for requests
0001 S_DOOR_OPENING Opening door, clearing current floor request
0010 S_DOOR_OPEN Door open, maintaining open command
0011 S_DOOR_CLOSING Closing door (door_controller manages)
0100 S_CHECK_REQ Evaluate requests, decide direction
0101 S_MOVING_UP Moving up, one floor per 1Hz tick
0110 S_MOVING_DOWN Moving down, one floor per 1Hz tick
0111 S_ARRIVED Arrived, check direction-aware stop logic
1000 S_RETURN_HOME Returning to 1F, interruptible
1001 S_ALARM Alarm active, all outputs quiesced

Clock Domains

graph LR
    SRC["50 MHz<br/><sub>System Clock</sub>"]

    SRC --> D1["1 Hz<br/><sub>Movement &amp; Door timing</sub>"]
    SRC --> D2["100 Hz<br/><sub>Debounce &amp; Requests</sub>"]
    SRC --> D3["500 Hz<br/><sub>Buzzer tone generation</sub>"]
    SRC --> D4["1 kHz<br/><sub>Reserved</sub>"]

    D1 --> M1["elevator_ctrl"]
    D1 --> M2["door_controller"]
    D1 --> M3["alarm_controller<br/><sub>(LED blink)</sub>"]
    D2 --> M4["debounce &times;10"]
    D2 --> M5["request_handler"]
    D2 --> M6["alarm_controller<br/><sub>(toggle logic)</sub>"]
    D3 --> M7["buzzer_driver"]

    style SRC fill:#E3F2FD,stroke:#1565C0,stroke-width:2px
    style D1 fill:#C8E6C9,stroke:#2E7D32
    style D2 fill:#FFF9C4,stroke:#F9A825
    style D3 fill:#FFCCBC,stroke:#BF360C
    style D4 fill:#E0E0E0,stroke:#757575
    style M1 fill:#E8F5E9,stroke:#2E7D32
    style M2 fill:#E8F5E9,stroke:#2E7D32
    style M3 fill:#E8F5E9,stroke:#2E7D32
    style M4 fill:#FFFDE7,stroke:#F9A825
    style M5 fill:#FFFDE7,stroke:#F9A825
    style M6 fill:#FFFDE7,stroke:#F9A825
    style M7 fill:#FBE9E7,stroke:#BF360C
Loading

I/O Pinout

Exact pin assignments for the GW48 board (Mode NO.5) are defined in quartus/elevator_top.qsf.

Inputs (12 pins)
Port Width Pin Active Description
clk 1 PIN_152 — 50MHz system clock
rst_n 1 PIN_18 Low Asynchronous reset
btn_up1 1 PIN_21 High Floor 1 up call
btn_up2 1 PIN_22 High Floor 2 up call
btn_dn2 1 PIN_37 High Floor 2 down call
btn_dn3 1 PIN_38 High Floor 3 down call
btn_go1 1 PIN_39 High Car select: go to floor 1
btn_go2 1 PIN_41 High Car select: go to floor 2
btn_go3 1 PIN_43 High Car select: go to floor 3
btn_open 1 PIN_112 High Manual door open
btn_close 1 PIN_126 High Manual door close
btn_alarm 1 PIN_161 High Alarm button
Outputs (12 pins)
Port Width Pin Active Description
seg7 7 PIN_56/57/63/68/69/70/73 Low 7-segment display (common anode, gfedcba)
led_up 1 PIN_127 High Up direction indicator
led_dn 1 PIN_128 High Down direction indicator
led_door 1 PIN_131 High Door open status
led_alarm 1 PIN_132 High Alarm LED (blinks 0.5Hz)
buzzer 1 PIN_164 High Buzzer output

Quick Start

The repository already contains a complete Quartus II 9.1 project:

1. Open quartus/elevator_top.qpf in Quartus II 9.1 (32-Bit)
2. Confirm the top-level entity is elevator_top (Project -> Set as Top-Level Entity)
3. Compile: Processing -> Start Compilation (or Ctrl+L)
4. Functional simulation: Processing -> Generate Functional Simulation Netlist,
   then Processing -> Start Simulation with quartus/elevator_ctrl_test1.vwf
5. Program the EP3C40Q240C8 via USB-Blaster and test on the board

For detailed simulation steps, see doc/quartus-ii-simulation-tutorial.md. For on-board programming, see doc/board-programming-tutorial.md and doc/ep3c40q240c8-烧录实操教程.md.

Project Structure

FPGA-Elevator-controller/
├── src/            # Canonical VHDL-93 source (9 modules)
├── quartus/        # Quartus II project (qpf/qsf) + VWF simulation
├── doc/            # Design documentation & tutorials
├── LICENSE         # MIT License
└── README.md

Documentation Index

Document Description
电梯控制器的设计.md Course design specification (requirements & grading)
architecture.md Module hierarchy, entity definitions, FSM design, signal interconnect, clock domains
scheduling-algorithm.md SCAN scheduling algorithm, request management, door control, special scenarios
research-report.md Research report: reference designs, design patterns, defense Q&A
quartus-ii-simulation-tutorial.md Step-by-step Quartus II 9.1 VWF simulation guide
quartus-ii-9.1-vhdl-research.md Quartus II 9.1 VHDL compatibility, synthesis rules, coding practices
compilation-and-generation.md Full compilation flow: checklist, report interpretation, .sof generation
board-programming-tutorial.md FPGA board programming & hardware testing (EP3C40Q240C8 + GW48)
quartus-ii-programmer-and-usb-blaster.md USB-Blaster driver install (Windows 11) and Programmer usage
quartus-ii-programming-tutorial-outline.md Programming tutorial structure outline & checklist
ep3c40q240c8-烧录实操教程.md EP3C40Q240C8 JTAG/EPCS hands-on programming guide
课程设计报告.md Final course design report

License

This project is licensed under the MIT License.

中文

项目简介

基于 CPLD/FPGA 的三层电梯控制器，采用 EDA 技术实现。项目使用 VHDL-93 语言，遵循自顶向下的层次化设计方法，完成综合、仿真及实际 FPGA 开发板部署。主控采用 10 状态 SCAN（电梯）调度算法 状态机，并配有独立的门控、请求处理与输出驱动子模块。

本项目为 EDA 技术课程设计作品。

功能特性

类别 功能 说明
基础 三层运行 上下行运动，含方向约束（1层无下行、3层无上行）
基础 门控系统 10秒自动开关门，支持手动开门/关门按钮
基础 楼层显示 七段数码管实时显示当前楼层
基础 空闲返回 无请求时自动返回1层待命
创新 报警系统 紧急报警，LED闪烁 + 蜂鸣器报警音
创新 到站提示 到达目标楼层时蜂鸣器短响0.5秒
创新 方向指示 上行/下行 LED 方向指示灯

技术栈

 语言          VHDL-93 (IEEE STD_LOGIC_1164, STD_LOGIC_UNSIGNED)
 EDA 工具      Quartus II 9.1 (32-Bit)
 目标器件      Cyclone III EP3C40Q240C8（240 引脚 PQFP）
 实验平台      康芯 GW48 系列（GW3C40 适配板，NO.5 模式）
 设计方法      自顶向下层次化设计，双进程状态机
 复位方式      异步低电平有效 (rst_n)
 引脚数        12 输入 + 12 输出 = 24 引脚

系统架构

graph TD
    subgraph TOP["elevator_top &mdash; 顶层实体"]
        direction TB

        CLK["clk_divider<br/><sub>50MHz &rarr; 1Hz / 100Hz / 500Hz / 1kHz</sub>"]

        subgraph INPUT["输入处理"]
            DEB["debounce &times;10<br/><sub>两级同步 + 计数消抖 + 边沿检测</sub>"]
            REQ["request_handler<br/><sub>3&times;3位请求寄存器组，SCAN调度支持</sub>"]
        end

        subgraph CONTROL["控制逻辑"]
            FSM["elevator_ctrl<br/><sub>10状态 SCAN 调度状态机</sub>"]
            DOOR["door_controller<br/><sub>4状态门控状态机，10秒定时器</sub>"]
        end

        subgraph OUTPUT["输出驱动"]
            DISP["display_driver<br/><sub>七段数码管译码器</sub>"]
            ALM["alarm_controller<br/><sub>报警切换 + LED闪烁</sub>"]
            BUZ["buzzer_driver<br/><sub>到站短响 + 报警长鸣</sub>"]
        end
    end

    CLK --> DEB
    DEB --> REQ
    REQ -- "req_up/dn/go<br/>any_request" --> FSM
    FSM -- "clear_req" --> REQ
    FSM -- "开/关门指令" --> DOOR
    DOOR -- "door_opened<br/>door_closed" --> FSM
    FSM -- "current_floor" --> DISP
    ALM -- "alarm_active" --> FSM
    ALM -- "buzzer_en" --> BUZ

    style TOP fill:#E3F2FD,stroke:#1565C0,stroke-width:2px,color:#0D47A1
    style INPUT fill:#E8F5E9,stroke:#2E7D32,stroke-width:1px
    style CONTROL fill:#FFF3E0,stroke:#E65100,stroke-width:1px
    style OUTPUT fill:#F3E5F5,stroke:#6A1B9A,stroke-width:1px
    style CLK fill:#BBDEFB,stroke:#1565C0
    style DEB fill:#C8E6C9,stroke:#2E7D32
    style REQ fill:#C8E6C9,stroke:#2E7D32
    style FSM fill:#FFE0B2,stroke:#E65100
    style DOOR fill:#FFE0B2,stroke:#E65100
    style DISP fill:#E1BEE7,stroke:#6A1B9A
    style ALM fill:#E1BEE7,stroke:#6A1B9A
    style BUZ fill:#E1BEE7,stroke:#6A1B9A
Loading

模块一览

模块 文件 行数 时钟域 说明
elevator_top elevator_top.vhd 617 全部 顶层集成，组件例化与信号互连
clk_divider clk_divider.vhd 132 50MHz 分频器：1Hz、100Hz、500Hz、1kHz
debounce debounce.vhd 99 100Hz 通用按键消抖，带边沿检测
request_handler request_handler.vhd 156 100Hz 请求寄存器组，清除优先于置位
elevator_ctrl elevator_ctrl.vhd 433 1Hz 主控状态机，10状态 SCAN 调度
door_controller door_controller.vhd 196 1Hz 门控状态机，10秒自动关门
display_driver display_driver.vhd 66 — 纯组合逻辑七段译码器
alarm_controller alarm_controller.vhd 88 100Hz+1Hz 报警切换，LED 以 0.5Hz 闪烁
buzzer_driver buzzer_driver.vhd 94 500Hz 双模式蜂鸣器：到站短响 + 报警音

状态机

主控制器 (elevator_ctrl) 实现了 10 状态 FSM，采用 SCAN（电梯）调度算法：

stateDiagram-v2
    [*] --> S_IDLE

    S_IDLE --> S_CHECK_REQ : 有请求
    S_IDLE --> S_RETURN_HOME : 空闲超时<br/>且不在1层

    S_CHECK_REQ --> S_DOOR_OPENING : 需要停靠
    S_CHECK_REQ --> S_MOVING_UP : 上方有请求 且 方向=上
    S_CHECK_REQ --> S_MOVING_DOWN : 下方有请求 且 方向=下

    S_MOVING_UP --> S_ARRIVED : 上移一层
    S_MOVING_DOWN --> S_ARRIVED : 下移一层

    S_ARRIVED --> S_DOOR_OPENING : 需要停靠
    S_ARRIVED --> S_MOVING_UP : 继续上行
    S_ARRIVED --> S_MOVING_DOWN : 继续下行

    S_DOOR_OPENING --> S_DOOR_OPEN : 立即转换
    S_DOOR_OPEN --> S_DOOR_CLOSING : 门已关闭
    S_DOOR_CLOSING --> S_CHECK_REQ : 关门完成

    S_RETURN_HOME --> S_MOVING_DOWN : 楼层 &gt; 1层
    S_RETURN_HOME --> S_IDLE : 到达1层 或 有新请求

    S_ALARM --> S_IDLE : 报警解除

    note right of S_ALARM
        最高优先级。
        任何状态在报警激活时
        均立即跳转至此。
    end note
Loading
编码 状态 说明
0000 S_IDLE 空闲等待，当前楼层待命
0001 S_DOOR_OPENING 开门中，清除当前楼层请求
0010 S_DOOR_OPEN 门已打开，保持开门指令
0011 S_DOOR_CLOSING 关门中（由 door_controller 自主管理）
0100 S_CHECK_REQ 检查请求，决定运行方向
0101 S_MOVING_UP 上行中，每个 1Hz 节拍移动一层
0110 S_MOVING_DOWN 下行中，每个 1Hz 节拍移动一层
0111 S_ARRIVED 到站，执行方向感知的停靠判断
1000 S_RETURN_HOME 返回1层，可被新请求中断
1001 S_ALARM 报警状态，所有输出静默

时钟域架构

graph LR
    SRC["50 MHz<br/><sub>系统时钟</sub>"]

    SRC --> D1["1 Hz<br/><sub>电梯运行 &amp; 门控定时</sub>"]
    SRC --> D2["100 Hz<br/><sub>按键消抖 &amp; 请求处理</sub>"]
    SRC --> D3["500 Hz<br/><sub>蜂鸣器音调生成</sub>"]
    SRC --> D4["1 kHz<br/><sub>预留</sub>"]

    D1 --> M1["elevator_ctrl"]
    D1 --> M2["door_controller"]
    D1 --> M3["alarm_controller<br/><sub>(LED闪烁)</sub>"]
    D2 --> M4["debounce &times;10"]
    D2 --> M5["request_handler"]
    D2 --> M6["alarm_controller<br/><sub>(切换逻辑)</sub>"]
    D3 --> M7["buzzer_driver"]

    style SRC fill:#E3F2FD,stroke:#1565C0,stroke-width:2px
    style D1 fill:#C8E6C9,stroke:#2E7D32
    style D2 fill:#FFF9C4,stroke:#F9A825
    style D3 fill:#FFCCBC,stroke:#BF360C
    style D4 fill:#E0E0E0,stroke:#757575
    style M1 fill:#E8F5E9,stroke:#2E7D32
    style M2 fill:#E8F5E9,stroke:#2E7D32
    style M3 fill:#E8F5E9,stroke:#2E7D32
    style M4 fill:#FFFDE7,stroke:#F9A825
    style M5 fill:#FFFDE7,stroke:#F9A825
    style M6 fill:#FFFDE7,stroke:#F9A825
    style M7 fill:#FBE9E7,stroke:#BF360C
Loading

引脚定义

具体引脚分配（GW48 实验箱 NO.5 模式）见 quartus/elevator_top.qsf。

输入端口（12 引脚）
端口 位宽 引脚 有效电平 说明
clk 1 PIN_152 — 50MHz 系统时钟
rst_n 1 PIN_18 低 异步复位
btn_up1 1 PIN_21 高 1层上行呼叫
btn_up2 1 PIN_22 高 2层上行呼叫
btn_dn2 1 PIN_37 高 2层下行呼叫
btn_dn3 1 PIN_38 高 3层下行呼叫
btn_go1 1 PIN_39 高 轿内选层：去1层
btn_go2 1 PIN_41 高 轿内选层：去2层
btn_go3 1 PIN_43 高 轿内选层：去3层
btn_open 1 PIN_112 高 手动开门
btn_close 1 PIN_126 高 手动关门
btn_alarm 1 PIN_161 高 报警按钮
输出端口（12 引脚）
端口 位宽 引脚 有效电平 说明
seg7 7 PIN_56/57/63/68/69/70/73 低 七段数码管（共阳极，gfedcba）
led_up 1 PIN_127 高 上行方向指示灯
led_dn 1 PIN_128 高 下行方向指示灯
led_door 1 PIN_131 高 开门状态指示灯
led_alarm 1 PIN_132 高 报警 LED（0.5Hz 闪烁）
buzzer 1 PIN_164 高 蜂鸣器输出

快速上手

仓库已包含完整的 Quartus II 9.1 工程：

1. 用 Quartus II 9.1 (32-Bit) 打开 quartus/elevator_top.qpf
2. 确认顶层实体为 elevator_top（Project -> Set as Top-Level Entity）
3. 编译：Processing -> Start Compilation（或 Ctrl+L）
4. 功能仿真：Processing -> Generate Functional Simulation Netlist，
   然后 Processing -> Start Simulation，使用 quartus/elevator_ctrl_test1.vwf
5. 通过 USB-Blaster 下载至 EP3C40Q240C8 并在实验箱上测试

详细仿真步骤请参阅 doc/quartus-ii-simulation-tutorial.md；板级下载请参阅 doc/board-programming-tutorial.md 与 doc/ep3c40q240c8-烧录实操教程.md。

项目结构

FPGA-Elevator-controller/
├── src/            # 规范 VHDL-93 源码（9 个模块）
├── quartus/        # Quartus II 工程（qpf/qsf）+ VWF 仿真
├── doc/            # 设计文档与教程
├── LICENSE         # MIT 许可证
└── README.md

文档索引

文档 说明
电梯控制器的设计.md 课程设计任务书（需求与评分要求）
architecture.md 模块层次、实体定义、状态机设计、信号互连、时钟域
scheduling-algorithm.md SCAN 调度算法、请求管理、门控逻辑、特殊场景分析
research-report.md 调研报告：参考方案、设计模式、答辩问答
quartus-ii-simulation-tutorial.md Quartus II 9.1 VWF 仿真分步指南
quartus-ii-9.1-vhdl-research.md Quartus II 9.1 VHDL 兼容性与编码规范
compilation-and-generation.md 完整编译流程：编译前检查、报告解读、.sof 生成
board-programming-tutorial.md 板级烧录与硬件测试（EP3C40Q240C8 + GW48）
quartus-ii-programmer-and-usb-blaster.md USB-Blaster 驱动安装（Windows 11）与 Programmer 使用
quartus-ii-programming-tutorial-outline.md 烧录教程结构大纲与检查清单
ep3c40q240c8-烧录实操教程.md EP3C40Q240C8 JTAG/EPCS 烧录实操指南
课程设计报告.md 最终课程设计报告

许可证

本项目基于 MIT License 开源。

Built with VHDL-93 for EDA Course Design

About

3-floor elevator controller in VHDL-93 for Cyclone III EP3C40Q240C8, built with Quartus II 9.1 - SCAN scheduling FSM, door control, alarm and buzzer.

Topics

cyclone-iiidigital-designedaelevator-controllerfpgaquartusvhdl

Resources

Readme
MIT license
Activity

Stars

0 stars

Watchers

0 watching

Forks

0 forks
Report repository

Releases

Packages

Contributors

Languages