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RTL Design | Verification
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RTL Design | Verification
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Rwtmanni17/README.md

Sarthak Rawat

Front-End VLSI | RTL Design | Functional Verification

Electronics and Communication Engineering undergraduate with a strong interest in Front-End VLSI Design. Focused on designing synthesizable RTL using Verilog HDL and building digital systems through hands-on implementation and verification.

Currently expanding expertise in SystemVerilog, Functional Verification, ASIC Design Flow, and FPGA-based Digital Design while developing practical projects that strengthen digital design fundamentals and industry-relevant skills.

🛠 Tech Stack

Verilog SystemVerilog Vivado Git GitHub Python

📈 Contribution Activity

🎯 Areas of Interest

  • RTL Design
  • Functional Verification
  • Digital Design
  • ASIC Front-End Design
  • FPGA Development

📫 Connect

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  1. UART UART Public

    RTL implementation of a UART using Verilog HDL with functional simulation and verification.

    Verilog

  2. Sequence_Detector_Project Sequence_Detector_Project Public

    FSM-based Sequence Detector implemented in Verilog HDL with simulation and verification.

    Verilog

  3. Traffic_light_controller_6state Traffic_light_controller_6state Public

    RTL implementation of a 6-State Traffic Light Controller using Verilog HDL with functional simulation and verification.

    Verilog

  4. Vending-Machine Vending-Machine Public

    FSM-based Vending Machine Controller implemented in Verilog HDL with simulation and verification.

    Verilog

  5. Synchronous-FIFO Synchronous-FIFO Public

    RTL implementation of a Synchronous FIFO using Verilog HDL with functional simulation and verification.

    Verilog 1