[DM/OFW][PCI] Fix address translation and PCI resource enumeration - #11677
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GuEe-GUI wants to merge 3 commits into
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[DM/OFW][PCI] Fix address translation and PCI resource enumeration#11677GuEe-GUI wants to merge 3 commits into
GuEe-GUI wants to merge 3 commits into
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Rework OFW address translation to walk nested bus ranges in the correct direction and cache "ranges" and "dma-ranges" independently. Handle PCI three-cell addresses without treating the PCI flags cell as part of the address, and fix CPU-to-DMA and DMA-to-CPU translation across nested buses. Fix PCI BAR sizing and assignment by disabling address decoding during probing, preserving BAR attribute bits, and programming 64-bit BARs correctly. Add device enable and disable helpers so resources and bus mastering are enabled before driver probe. Program bridge memory and prefetch windows while scanning downstream buses, correctly link child buses into the PCI bus hierarchy, and avoid unnecessary PCIe link retraining when the link is already active. Allow host bridges without a device-tree pci-domain property by allocating unique domains dynamically, while preserving explicit domain assignments. Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity selection. Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices. Signed-off-by: GuEe-GUI <2991707448@qq.com>
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📌 Code Review Assignment🏷️ Tag: componentsReviewers: @Maihuanyi Changed Files (Click to expand)
📊 Current Review Status (Last Updated: 2026-08-07 09:44 CST)
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Pull request overview
This PR updates RT-Thread’s PCI/OFW stack to improve device-tree address translation (including nested bus ranges and PCI 3-cell addresses), PCI resource (BAR) enumeration/assignment, bridge window programming, and MSI/MSI-X setup. It also adds the Raspberry Pi PCI vendor ID for RP1/downstream devices.
Changes:
- Rework OFW
ranges/dma-rangesparsing, caching, and translation to better support nested buses and PCI address cell formats. - Fix PCI BAR sizing/assignment flow and add enable/disable helpers to ensure decoding and bus mastering are set appropriately around driver probe.
- Improve bridge scanning behavior (windows programming, hierarchy linking) and adjust MSI/MSI-X IRQ setup logic.
PR Checklist Notes / PR 检查项备注:
- 🟡 [PR Title/PR 标题]: Title prefix is not lowercase (
[DM/OFW][PCI] ...).
English: Suggested title format in lowercase:[dm/ofw][pci] Fix address translation and PCI resource enumeration.
中文：标题前缀建议使用小写，例如：[dm/ofw][pci] Fix address translation and PCI resource enumeration。
Reviewed changes
Copilot reviewed 10 out of 10 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| components/drivers/pci/probe.c | Allocate/take PCI domains dynamically and adjust bridge scanning (including bridge window programming). |
| components/drivers/pci/pci.c | Add rt_pci_enable_device() / rt_pci_disable_device() and refine resource/BAR handling around probe. |
| components/drivers/pci/pci_ids.h | Add Raspberry Pi PCI vendor ID. |
| components/drivers/pci/ofw.c | Make pci-domain optional and parse/cache ranges vs dma-ranges independently. |
| components/drivers/pci/msi/msi.c | Refine MSI/MSI-X vector addressing and affinity handling. |
| components/drivers/pci/msi/irq.c | Fix MSI/MSI-X IRQ allocation, error paths, and logging context. |
| components/drivers/ofw/ofw_internal.h | Extend cached bus-ranges metadata to include the range property type. |
| components/drivers/ofw/io.c | Rework address translation to walk nested ranges and support PCI 3-cell addresses. |
| components/drivers/include/drivers/pci.h | Export new PCI enable/disable APIs and adjust declarations/formatting. |
| components/drivers/include/drivers/ofw_io.h | Update CPU↔DMA translation helpers to use new translation behavior. |
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| rt_pci_read_config_u16(pdev, PCIR_SUBCLASS, &subclass); | ||
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| if (subclass == PCIS_DISPLAY_VGA) | ||
| { | ||
| cmd |= PCIM_CMD_PORTEN; | ||
| } |
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| rt_inline rt_uint64_t rt_ofw_translate_dma2cpu(struct rt_ofw_node *np, rt_uint64_t address) | ||
| { | ||
| rt_uint64_t bus_addr, cpu_addr; | ||
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| bus_addr = rt_ofw_reverse_address(np, "dma-ranges", address); | ||
| cpu_addr = rt_ofw_translate_address(np, "ranges", bus_addr); | ||
| cpu_addr = rt_ofw_translate_address(np, "dma-ranges", address); |
Comment on lines
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+1007
| if (host_bridge && host_bridge->root_bus) | ||
| { | ||
| rt_pci_enum_device(host_bridge->root_bus, pci_remove_bus_device, RT_NULL); | ||
| host_bridge->root_bus = RT_NULL; | ||
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| if (host_bridge->domain != RT_UINT32_MAX) | ||
| { | ||
| rt_dm_ida_free(&pci_domain_ida, host_bridge->domain); | ||
| } |
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| struct rt_ofw_node *bus; | ||
| struct rt_ofw_node *parents[16]; | ||
| int count = 0; |
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拉取/合并请求描述：(PR description)
[
Rework OFW address translation to walk nested bus ranges in the correct direction and cache "ranges" and "dma-ranges" independently. Handle PCI three-cell addresses without treating the PCI flags cell as part of the address, and fix CPU-to-DMA and DMA-to-CPU translation across nested buses.
Fix PCI BAR sizing and assignment by disabling address decoding during probing, preserving BAR attribute bits, and programming 64-bit BARs correctly. Add device enable and disable helpers so resources and bus mastering are enabled before driver probe.
Program bridge memory and prefetch windows while scanning downstream buses, correctly link child buses into the PCI bus hierarchy, and avoid unnecessary PCIe link retraining when the link is already active.
Allow host bridges without a device-tree pci-domain property by allocating unique domains dynamically, while preserving explicit domain assignments.
Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity selection.
Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices.
]
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我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up