Bridging the gap between silicon and software.
I am an engineering enthusiast currently pursuing a dual degree in B.E. (Hons.) Electronics & Instrumentation and M.Sc. Biological Sciences at BITS Pilani.
I thrive at the intersection of low-level hardware architecture and high-level software engineering—whether I'm executing full ASIC physical design flows, writing bare-metal firmware, or architecting scalable, LLM-powered backend pipelines.
- Software & AI: Python, Java, C/C++, Spring Boot, MySQL, LLMs, RAG Pipelines, NLP
- Hardware & Embedded: Verilog (RTL), Embedded C, Cadence (Genus/Innovus), Xilinx (Vivado/Vitis)
- Core Domains: Full-Stack Backend, Prompt Engineering, ASIC Physical Design, SoC Architecture, Bare-Metal Programming
- 🧠 LLM-Based Code Evaluator: Engineered a rigorous prompt-engineering pipeline evaluating 230+ complex code submissions with 92% logic accuracy.
- 🏥 Digital Medical Receipt Backend: Architected a secure Java Spring Boot REST API for clinical environments, featuring RBAC, JWT, and OpenFDA integration.
- 🖨️ Image Processing Toolkit: Built an automated OCR data pipeline using OpenCV and PaddleOCR to digitize varied unstructured documents with >95% accuracy.
- 🏢 RTL-to-GDSII Physical Design: Executed a full ASIC physical design flow using Cadence Genus and Innovus, optimizing floorplanning, power routing, CTS, and NanoRoute for tape-out readiness.
- ⚡ 32-bit RISC-V CPU: Designed a custom RV32I single-cycle processor in Verilog, built from the ground up to execute I/R-type instructions.
- 🛰️ Bare-Metal Telemetry: Engineered a dual-node STM32F407 system handling a 168MHz PLL and raw hardware peripheral (SPI/I2C/UART) manipulation with zero HAL overhead.
When I'm not compiling code or synthesizing RTL, I'm likely:
- 🎥 Directing productions as the Video and Short Film Coordinator (VaSCo) for the BITS Pilani Film Making Club.
- 🏋️♂️ Chasing personal bests in powerlifting, playing table tennis, or unwinding with a good movie.
