[Common] Let MXFP8 quantization always reduce dbias in colwise - #3439
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kainzhong wants to merge 2 commits into
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[Common] Let MXFP8 quantization always reduce dbias in colwise#3439kainzhong wants to merge 2 commits into
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Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
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Greptile SummaryThe PR moves most fused MXFP8 dbias reductions to the columnwise traversal while retaining the rowwise path for the FP32 activation case.
Confidence Score: 5/5The PR appears safe to merge. No blocking failure remains. Important Files Changed
Flowchart%%{init: {'theme': 'neutral'}}%%
flowchart TD
A[MXFP8 quantization with fused dbias] --> B{Columnwise scaling enabled?}
B -->|Yes| C[Columnwise quantization and dbias reduction]
B -->|No| D{FP32 input with activation?}
D -->|Yes| E[Rowwise quantization and dbias reduction]
D -->|No| F[Columnwise dbias-only pass]
F --> G[Cache fused activation when needed]
G --> H[Rowwise quantization consumes cache]
C --> I[Write partial dbias workspace]
E --> I
F --> I
Reviews (2): Last reviewed commit: "fix" | Re-trigger Greptile |
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Description
This PR improve MXFP8 kernel's performance for DBIAS reduction by disabling row-wise DBIAS reduction and letting column-wise do it instead. By doing this we can eliminate the row-wise reduction register array and skip the thread data exchange where each thread owns a column instead of the row it had after the row-wise quantization, and reduce this column fragment and write the result in the workspace buffer.
The only exception is when we have FP32+DBIAS+DACT, where registers are no longer bottleneck, so this optimization's cost (extra SMEM traffic when we cache activations in the column-wise reduction only pass) is more than its gain (register save doesn't alleviate the bottleneck) so we disable it for this case only.
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