Name		Name	Last commit message	Last commit date
header		header
src		src
.gitattributes		.gitattributes
.gitignore		.gitignore
README.md		README.md
bus.h.v		bus.h.v
bus.v		bus.v
bus_addr_dec.v		bus_addr_dec.v
bus_arbiter.v		bus_arbiter.v
bus_master_mux.v		bus_master_mux.v
bus_slave_mux.v		bus_slave_mux.v
cpu.h		cpu.h
global_config.h		global_config.h
global_config.h.v		global_config.h.v
isa.h		isa.h
lomot.v		lomot.v
nettype.h.v		nettype.h.v
stddef.h.v		stddef.h.v

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lomotFPGA

a verilog project about how to make a CPU

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a verilog project about how to make a CPU

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