docs(verification): define verifier kernel proof plan - #436
Conversation
PR SummaryLow Risk Overview The spec is not a protocol proof. It defines six claim layers, a target registry (NTT/CRT matvec, deferred fp128, sampling, operator-norm), and a verified dispatch policy: AVX2 or scalar on x86 (no IFMA52), NEON on AArch64, scalar on RISC-V. Proofs must match linked production bytes; constant-time is explicitly out of scope. Also wires Reviewed by Cursor Bugbot for commit 7082cf5. Bugbot is set up for automated code reviews on this repo. Configure here. |
Documentation blast radius (advisory)These regions may need doc/spec/book updates based on changed paths. Changed files in this PR: 4
|
PCS Profile Benchmark
13 of 13 profiles passed. Times are medians of Each sample verifies the same proof first with the configured multi-threaded pool and then with one thread. Both timings reuse the same verifier setup. Merge-base comparisons are available for Benchmark shards
Public opening statements
One-hot profiles generate deterministic witnesses with one Direct evaluates the public setup contribution during Stage 2. Recursive carries the same check through a Stage 3 setup-product sumcheck. Both modes execute the complete fold schedule and terminal verification. The chunked profiles Generated profiles may select different A, B, and D ring dimensions at different fold levels. The short profile names omit those dimensions. Each sample generates deterministic witnesses and opening points, prepares setup, commits, proves, serializes the proof, checks its size, prepares verifier setup, and verifies the claimed openings. It does not test malformed proofs. Phase time
Proof size and protocol shape
Grinding retries are rejected attempts at each fold, listed in measured-run order. Zero means the first sampled nonce was accepted. Memory and setup size
Deltas are shown only for profiles with a matching merge-base case. Negative is smaller or faster. The uploaded |
CI test timing
Run summary
Wall time spans 2 parallel nextest slice shards. Slowest tests
Regressions vs mainNo per-test regressions above the threshold. New slow testsNo new tests ≥30s vs main baseline. |
Point the verifier kernel proof plan at the exact combined s2n-bignum fork revision. Record the four available instruction model families and keep complete kernel, linkage, and dispatch claims open.
Summary
This PR proposes the formal verification plan for the low-level arithmetic used by the Akita verifier.
It does not change runtime code. It defines the targets, proof claims, dispatch rules, linkage checks, performance gates, and staged implementation work needed before Akita can claim that its production verifier kernels are proved down to machine code.
The proof plan now pins the combined s2n-bignum model revision
db6d2002554d02a78cb4d6c183f16ecd75395691. This fork revision contains the initial AVX2 and NEON instruction semantics needed to begin the kernel proofs.Why this is needed
The verifier currently relies on optimized CRT and NTT code, deferred fp128 accumulation, sparse challenge sampling, and a fixed-point operator-norm predicate. These paths have scalar differential tests, bounds checks, and security certificates, but most do not have a theorem about the exact instructions linked into the verifier binary.
The current exact fp128 path can also choose AVX-512 IFMA52 on capable x86 machines. The pinned s2n-bignum model has strong AVX2 and NEON proof support, but it does not model the IFMA52 path. A precise production policy is therefore needed before proof implementation starts.
Proposed design
The spec defines six claim layers for each kernel.
The verified x86 profile uses AVX2 when available and a proved scalar symbol otherwise. It never selects AVX-512 IFMA52. This rule applies only to verifier-reachable cache construction and execution. The prover may keep IFMA52.
The AArch64 profile uses NEON with a proved scalar fallback where one remains supported. The RISC-V profile uses proved scalar objects and keeps the prepared cache artifact inside the stated setup and schedule binding.
Proof targets
The target registry covers:
ISA audit findings
The pinned fork is based on upstream s2n-bignum revision
ac31a43db30953037abd1b64b540e65cf31f4c67. It adds the four instruction families found missing by the source audit.VPSHUFHWandVPSHUFLWfor the AVX2 i16 lane shuffles.VPMOVSXBWfor signed i8 to i16 widening.LD4andST4structure operations.SHSUBsigned halving subtraction.These PRs define and test instruction semantics. They do not prove the complete NTT, Montgomery multiplication, ABI symbol, linked object, or runtime dispatch. The exact production disassembly remains the source of truth because intrinsics do not fix the compiler's instruction choice.
Each extension still needs upstream review. The production proof profile records the fork while review is pending and must return to an upstream revision after acceptance.
Important boundaries
The spec keeps distinct claims separate.
Performance policy
The proposed large NTT symbols are out of line, but each call covers a complete transform, pointwise row dot, or matrix row. The spec forbids per-butterfly call boundaries.
Every replacement requires a named benchmark, raw before and after results, and an end-to-end verifier profile. The default limit is a two percent median regression unless maintainers approve the measured tradeoff. The IFMA52 to AVX2 verifier change must be measured on machines that currently select IFMA52.
Reviewer map
specs/verifier-hol-light-kernels.mdcontains the complete goal, trust boundary, target registry, proof shape, implementation stages, tests, and performance gates.specs/PRUNING.mdadds the proposal to the live specification set.book/src/foundations/spec-index.mdexposes the new live proposal in the Book index.scripts/check-spec-references.shincludes the spec in the default dead-symbol scan.Validation
./scripts/check-doc-guardrails.sh./scripts/check-spec-references.shtypos specs/verifier-hol-light-kernels.mdgit diff --checkAll commands pass locally.
Deferred work
This PR contains no proof objects and changes no production dispatch. The acceptance list remains open. The initial instruction definitions are available, but complete kernel theorems, upstream model review, standalone symbol boundaries, the x86 policy, and performance measurements remain deferred.