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License?

Status: Open.

#6 In Arlet/verilog-6502;

· anders-code opened on Oct 4, 2024

ALU is a name conflict with GOWIN FPGAs

Status: Open.

#5 In Arlet/verilog-6502;

· stacksmith opened on Aug 11, 2024

Write (WE) active during reset

Status: Open.

#4 In Arlet/verilog-6502;

· jesari-git opened on Feb 1, 2024

Verilator build warnings

Status: Open.

#2 In Arlet/verilog-6502;

· kallisti5 opened on Oct 23, 2014