Commit dd10eef
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regalloc: model exception-handler edges in liveness
A try body lowers to blocks whose only explicit CFG successors are the
normal-flow ones (e.g. RAISE_VARARGS -> exit); the edge from a faulting op
in the try body to the handler is implicit (established by SETUP_EXC_HANDLE
in the *predecessor*). mlir::Liveness therefore never sees body-op ->
handler, so a value that is live at the handler — or live after it — was
considered dead inside the try body, and the register allocator happily
reused its register there.
When an exception actually unwound, that register had been overwritten.
The clearest case: a `for` loop whose body contains `try/except`. The
FOR_ITER iterator is read again after the handler (next iteration), but its
register was reused for a value inside the try body, so the resumed loop
read a clobbered iterator (abort in ForIter / "object is not an iterator").
The same bug corrupted exception args across sequential try/except blocks.
Fix: in LiveAnalysis, for every block in a try body (those dominated by the
SETUP_EXC_HANDLE / SETUP_WITH try-entry successor), add the handler's
live-in set to the block's live-out before computing per-op liveness. Any
op in the try body can transfer to the handler, so values live at the
handler are live across the whole try body. Dominance keeps it bounded and
handles nesting; the pass is skipped entirely when a function has no
handlers.
This makes the iterator (and any value live past the handler) interfere
with try-body temporaries, so they no longer share a register.1 parent 8d38a64 commit dd10eef
5 files changed
Lines changed: 337 additions & 36 deletions
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- integration/tests
- src/executable/mlir/Target/PythonBytecode
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