From d27ab7765f643883f221a0382f11385d2343939b Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Sat, 1 Aug 2026 22:45:41 +0800 Subject: [PATCH 1/6] [dm][dma] update DMA interface Extend DMA mapping to honor OFW dma-ranges even when no reserved memory pool is present, and add PCI host-bridge DMA-region translation for PCI devices. Prefer 32-bit-addressable allocations for translated devices, improve pool allocation fallbacks and synchronization, and establish a linear mapping for installed DMA pools when possible. Signed-off-by: GuEe-GUI <2991707448@qq.com> --- bsp/qemu-virt64-aarch64/README.md | 10 +- bsp/qemu-virt64-aarch64/README_zh.md | 10 +- bsp/qemu-virt64-aarch64/amp.dtsi | 2 +- components/drivers/dma/dma_pool.c | 305 +++++++++++++++++++++++++-- libcpu/aarch64/common/setup.c | 77 ++++++- 5 files changed, 377 insertions(+), 27 deletions(-) diff --git a/bsp/qemu-virt64-aarch64/README.md b/bsp/qemu-virt64-aarch64/README.md index 8ac4012c1caa..a4353865bc9e 100644 --- a/bsp/qemu-virt64-aarch64/README.md +++ b/bsp/qemu-virt64-aarch64/README.md @@ -191,10 +191,10 @@ VirtIO Sound: AMP heterogeneous multi-core (RPMSG slave, **requires Smart version**): ``` -./qemu.py -dtbo amp.dtsi -mem 258 +./qemu.py -dtbo amp.dtsi -mem 300 ``` -> **Note**: The AMP demo requires the **Smart version** (`RT_USING_SMART`) and **`-mem 258`** (memory layout in `amp.dtsi` needs ~258 MB; the default 128 MB is insufficient). `qemu.py` also increments `-smp` by 1 when `amp_soc` is detected (e.g. `RT_CPUS_NR=4` runs as `-smp 5`). QEMU `loader` pre-loads `amp.dtb` and `rtthread.bin` to fixed physical addresses in `amp.dtsi` (e.g. `kernel-entry = 0x48480000`); the primary core then starts the slave via PSCI. The standard kernel must run in a region where virtual addresses equal physical addresses and cannot be used for the slave address space. Enable Smart in menuconfig and rebuild. +> **Note**: The AMP demo requires the **Smart version** (`RT_USING_SMART`) and **`-mem 300`** (memory layout in `amp.dtsi` needs ~300 MB; the default 128 MB is insufficient). `qemu.py` also increments `-smp` by 1 when `amp_soc` is detected (e.g. `RT_CPUS_NR=4` runs as `-smp 5`). QEMU `loader` pre-loads `amp.dtb` and `rtthread.bin` to fixed physical addresses in `amp.dtsi` (e.g. `kernel-entry = 0x48480000`); the primary core then starts the slave via PSCI. The standard kernel must run in a region where virtual addresses equal physical addresses and cannot be used for the slave address space. Enable Smart in menuconfig and rebuild. Camera demo (requires `-graphic` for framebuffer overlay in `camera.c`): @@ -328,12 +328,12 @@ Default application. Prints `hello rt-thread` after boot, then enters msh. QEMU `loader` pre-loads `amp.dtb` and `rtthread.bin` to addresses in `amp.dtsi`; the primary core then boots the slave CPU via the `amp_soc` devicetree node and PSCI. Primary and slave communicate through VirtIO RPMSG and Mailbox. The primary writes VirtIO Block `vdb` resource info into the slave DTB before starting the slave. `qemu.py` increments `-smp` by 1 for the extra CPU. -**Version requirement**: **Smart version** required (`RT_USING_SMART` in menuconfig), plus **`-mem 258`**. The standard kernel must run with virtual addresses equal to physical addresses. The AMP slave is loaded into a separate physical memory region (see `amp_memory`, `kernel-entry` in `amp.dtsi`), which violates that constraint — the standard kernel cannot be used for AMP demos. +**Version requirement**: **Smart version** required (`RT_USING_SMART` in menuconfig), plus **`-mem 300`**. The standard kernel must run with virtual addresses equal to physical addresses. The AMP slave is loaded into a separate physical memory region (see `amp_memory`, `kernel-entry` in `amp.dtsi`), which violates that constraint — the standard kernel cannot be used for AMP demos. Startup: ``` -./qemu.py -dtbo amp.dtsi -mem 258 +./qemu.py -dtbo amp.dtsi -mem 300 ``` Slave console: `telnet localhost 4323`. @@ -396,6 +396,6 @@ Optional VirtIO device arguments (add in `qemu.py` as needed): - GIC auto-switches to v3 when exceeding 8 cores; or specify `-gic 3` manually. `gic-version=max` is set only internally when using `-el 2` with GICv3. - 9P directory sharing requires QEMU built with virtfs (`--enable-virtfs`). - `-gl` requires QEMU built with OpenGL / VirGL (`--enable-opengl`, `--enable-virglrenderer`); this is independent of RT-Thread OpenGL support — the default software stack is 2D graphics only. -- AMP (`-dtbo`) requires Smart kernel (`RT_USING_SMART`), `-mem 258`, and auto-increments CPU count; the standard kernel requires VA=PA and cannot be used with slave images loaded at fixed physical addresses. +- AMP (`-dtbo`) requires Smart kernel (`RT_USING_SMART`), `-mem 300`, and auto-increments CPU count; the standard kernel requires VA=PA and cannot be used with slave images loaded at fixed physical addresses. - `-camera` requires a host V4L2 device path, Linux, and libvfio-user; your user must have read access to the device (typically via the `video` group); `-graphic` is needed only for the `camera.c` framebuffer preview demo. - Override root device or boot parameters via `-bootargs`. diff --git a/bsp/qemu-virt64-aarch64/README_zh.md b/bsp/qemu-virt64-aarch64/README_zh.md index 0b623627d834..3b93d5402892 100644 --- a/bsp/qemu-virt64-aarch64/README_zh.md +++ b/bsp/qemu-virt64-aarch64/README_zh.md @@ -187,10 +187,10 @@ VirtIO Sound 音频： AMP 异构多核（RPMSG 从核，**须 Smart 版本**）： ``` -./qemu.py -dtbo amp.dtsi -mem 258 +./qemu.py -dtbo amp.dtsi -mem 300 ``` -> **说明**：AMP 示例要求启用 **Smart 版本**（`RT_USING_SMART`），且必须使用 **`-mem 258`**（`amp.dtsi` 内存布局约需 258 MB，默认 128 MB 不足）。`qemu.py` 检测到 `amp_soc` 时会将 `-smp` 自动加 1（例如 `RT_CPUS_NR=4` 时实际以 `-smp 5` 启动）。QEMU `loader` 会预先将 `amp.dtb` 与 `rtthread.bin` 加载到 `amp.dtsi` 指定的固定物理地址（如 `kernel-entry = 0x48480000`），主核再通过 PSCI 拉起从核。标准版内核要求在虚拟地址与物理地址相等的区域运行，无法用于从核地址空间。请在 menuconfig 中开启 Smart 后重新编译。 +> **说明**：AMP 示例要求启用 **Smart 版本**（`RT_USING_SMART`），且必须使用 **`-mem 300`**（`amp.dtsi` 内存布局约需 300 MB，默认 128 MB 不足）。`qemu.py` 检测到 `amp_soc` 时会将 `-smp` 自动加 1（例如 `RT_CPUS_NR=4` 时实际以 `-smp 5` 启动）。QEMU `loader` 会预先将 `amp.dtb` 与 `rtthread.bin` 加载到 `amp.dtsi` 指定的固定物理地址（如 `kernel-entry = 0x48480000`），主核再通过 PSCI 拉起从核。标准版内核要求在虚拟地址与物理地址相等的区域运行，无法用于从核地址空间。请在 menuconfig 中开启 Smart 后重新编译。 摄像头演示（`camera.c` 叠加画面到 framebuffer，需配合 `-graphic`）： @@ -324,12 +324,12 @@ Linux 下需预先配置 TAP 网桥，Windows / WSL 下 TAP 支持有限。TAP QEMU `loader` 预先将 `amp.dtb` 与 `rtthread.bin` 加载到 `amp.dtsi` 指定地址，主核再通过 `amp_soc` 设备树节点与 PSCI 拉起从核 CPU。主从之间通过 VirtIO RPMSG + Mailbox 通信。主核将 VirtIO Block `vdb` 的资源信息写入从核 DTB 后启动从核。`qemu.py` 会为这颗额外 CPU 将 `-smp` 加 1。 -**版本要求**：须 **Smart 版本**（menuconfig 中 `RT_USING_SMART`），且须使用 **`-mem 258`**。标准版内核必须在虚拟地址与物理地址一致的映射下运行；AMP 从核加载到独立物理内存区域（见 `amp.dtsi` 中 `amp_memory`、`kernel-entry` 等），不满足该约束，因此标准版无法用于 AMP 演示。 +**版本要求**：须 **Smart 版本**（menuconfig 中 `RT_USING_SMART`），且须使用 **`-mem 300`**。标准版内核必须在虚拟地址与物理地址一致的映射下运行；AMP 从核加载到独立物理内存区域（见 `amp.dtsi` 中 `amp_memory`、`kernel-entry` 等），不满足该约束，因此标准版无法用于 AMP 演示。 启动方式： ``` -./qemu.py -dtbo amp.dtsi -mem 258 +./qemu.py -dtbo amp.dtsi -mem 300 ``` 从核控制台：`telnet localhost 4323`。 @@ -392,6 +392,6 @@ VirtIO 设备可选参数（在 `qemu.py` 中按需添加）： - 超过 8 核时 GIC 自动切换为 v3，也可手动指定 `-gic 3`。`gic-version=max` 仅在 `-el 2` 且 GICv3 时由脚本内部设置。 - 启用 9P 目录共享需 QEMU 编译时包含 virtfs（`--enable-virtfs`）。 - 使用 `-gl` 需 QEMU 编译时包含 OpenGL / VirGL（`--enable-opengl`、`--enable-virglrenderer`）；这与 RT-Thread 是否支持 OpenGL 无关，当前软件栈默认仅 2D 图形。 -- AMP（`-dtbo`）须 Smart 版本内核（`RT_USING_SMART`）、`-mem 258`，且自动增加 CPU 数；标准版要求 VA=PA 运行，无法用于从核固定物理地址加载场景。 +- AMP（`-dtbo`）须 Smart 版本内核（`RT_USING_SMART`）、`-mem 300`，且自动增加 CPU 数；标准版要求 VA=PA 运行，无法用于从核固定物理地址加载场景。 - `-camera` 须传入宿主机 V4L2 设备路径，仅支持 Linux，且需 libvfio-user；当前用户须能访问该设备（通常加入 `video` 组）；`-graphic` 仅 `camera.c` framebuffer 预览演示需要。 - 修改根设备或启动参数时，通过 `-bootargs` 覆盖默认参数。 diff --git a/bsp/qemu-virt64-aarch64/amp.dtsi b/bsp/qemu-virt64-aarch64/amp.dtsi index 2491d1b8a33f..01ff9491d96d 100755 --- a/bsp/qemu-virt64-aarch64/amp.dtsi +++ b/bsp/qemu-virt64-aarch64/amp.dtsi @@ -19,7 +19,7 @@ #define AMP_MEMORY_SIZE (128 * SIZE_MB) /* - * RUN COMMAND: ./qemu.py -dtbo amp.dtsi -mem 258 + * RUN COMMAND: ./qemu.py -dtbo amp.dtsi -mem 300 * REMOTE: telnet localhost 4323 */ diff --git a/components/drivers/dma/dma_pool.c b/components/drivers/dma/dma_pool.c index 79b89e39a297..88045b0851d0 100644 --- a/components/drivers/dma/dma_pool.c +++ b/components/drivers/dma/dma_pool.c @@ -31,6 +31,7 @@ #define DBG_LVL DBG_INFO #include +#include #include #include #include @@ -39,6 +40,7 @@ static RT_DEFINE_SPINLOCK(dma_pools_lock); static rt_list_t dma_pool_nodes = RT_LIST_OBJECT_INIT(dma_pool_nodes); static struct rt_dma_pool *dma_pool_install(rt_region_t *region); +static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool); static void *dma_alloc(struct rt_device *dev, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags); @@ -202,7 +204,10 @@ rt_inline rt_ubase_t ofw_addr_dma2cpu(struct rt_device *dev, rt_ubase_t addr) static void *ofw_dma_map_alloc(struct rt_device *dev, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - void *cpu_addr = dma_alloc(dev, size, dma_handle, flags); + void *cpu_addr; + + flags |= RT_DMA_F_32BITS; + cpu_addr = dma_alloc(dev, size, dma_handle, flags); if (cpu_addr && dma_handle) { @@ -302,17 +307,37 @@ static const struct rt_dma_map_ops ofw_dma_map_ops = { .sync_in_data = ofw_dma_map_sync_in_data, }; +static rt_bool_t ofw_node_has_dma_ranges(struct rt_ofw_node *np) +{ + struct rt_ofw_node *bus; + + for (bus = np ? np->parent : RT_NULL; bus; bus = bus->parent) + { + rt_ssize_t len; + + if (rt_ofw_get_prop(bus, "dma-ranges", &len) && len) + { + return RT_TRUE; + } + } + + return RT_FALSE; +} + /** - * @brief Determine DMA operations for a device tree device with memory-region + * @brief Determine DMA operations for a device tree device * * Parses the "memory-region" property to install DMA pools from * reserved-memory nodes. Sets RT_DMA_F_NOMAP if "no-map" is set, * and RT_DMA_F_NOCACHE if the device is not DMA-coherent. * + * Also installs ofw_dma_map_ops when the parent bus chain provides + * "dma-ranges", so CPU physical addresses are translated for DMA. + * * @param[in] dev Device to configure DMA operations for * - * @return Pointer to DMA map ops (ofw_dma_map_ops) if regions were found, - * RT_NULL otherwise + * @return Pointer to DMA map ops (ofw_dma_map_ops) when translation + * or memory-region pools apply, RT_NULL otherwise */ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) { @@ -332,12 +357,7 @@ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) if (!(mem_np = rt_ofw_find_node_by_phandle(phandle))) { - if (region_nr == 0) - { - return RT_NULL; - } - - break; + continue; } if ((err = rt_ofw_get_address(mem_np, 0, &addr, &size))) @@ -374,7 +394,7 @@ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) ++region_nr; } - if (region_nr) + if (region_nr || ofw_node_has_dma_ranges(np)) { ops = &ofw_dma_map_ops; } @@ -383,14 +403,198 @@ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) } #endif /* RT_USING_OFW */ +#ifdef RT_USING_PCI +static struct rt_pci_host_bridge *pci_device_host_bridge(struct rt_device *dev) +{ + struct rt_pci_device *pdev = rt_container_of(dev, struct rt_pci_device, parent); + + return rt_pci_find_host_bridge(pdev->bus); +} + +static rt_uint64_t pci_host_cpu_to_bus(struct rt_pci_host_bridge *host_bridge, rt_uint64_t cpu_addr) +{ + if (!host_bridge || !host_bridge->dma_regions) + { + return ~0ULL; + } + + for (int i = 0; i < host_bridge->dma_regions_nr; ++i) + { + struct rt_pci_bus_region *region = &host_bridge->dma_regions[i]; + + if (cpu_addr >= region->cpu_addr && + cpu_addr < region->cpu_addr + region->size) + { + return region->phy_addr + (cpu_addr - region->cpu_addr); + } + } + + return ~0ULL; +} + +static rt_uint64_t pci_host_bus_to_cpu(struct rt_pci_host_bridge *host_bridge, rt_uint64_t pci_addr) +{ + if (!host_bridge || !host_bridge->dma_regions) + { + return ~0ULL; + } + + for (int i = 0; i < host_bridge->dma_regions_nr; ++i) + { + struct rt_pci_bus_region *region = &host_bridge->dma_regions[i]; + + if (pci_addr >= region->phy_addr && pci_addr < region->phy_addr + region->size) + { + return region->cpu_addr + (pci_addr - region->phy_addr); + } + } + + return ~0ULL; +} + +static rt_ubase_t pci_addr_cpu2dma(struct rt_device *dev, rt_ubase_t addr) +{ + rt_uint64_t pci_dma; + struct rt_pci_host_bridge *host_bridge = pci_device_host_bridge(dev); + + if (!host_bridge) + { + return addr; + } + + pci_dma = pci_host_cpu_to_bus(host_bridge, addr); + + return pci_dma == ~0ULL ? addr : (rt_ubase_t)pci_dma; +} + +static rt_ubase_t pci_addr_dma2cpu(struct rt_device *dev, rt_ubase_t addr) +{ + rt_uint64_t cpu_addr; + struct rt_pci_host_bridge *host_bridge = pci_device_host_bridge(dev); + + if (!host_bridge) + { + return addr; + } + + cpu_addr = pci_host_bus_to_cpu(host_bridge, addr); + + return cpu_addr == ~0ULL ? addr : (rt_ubase_t)cpu_addr; +} + +static void *pci_dma_map_alloc(struct rt_device *dev, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + void *cpu_addr; + + flags |= RT_DMA_F_32BITS; + cpu_addr = dma_alloc(dev, size, dma_handle, flags); + + if (cpu_addr && dma_handle) + { + *dma_handle = pci_addr_cpu2dma(dev, *dma_handle); + } + + return cpu_addr; +} + +static void pci_dma_map_free(struct rt_device *dev, rt_size_t size, + void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags) +{ + dma_handle = pci_addr_dma2cpu(dev, dma_handle); + + dma_free(dev, size, cpu_addr, dma_handle, flags); +} + +static rt_err_t pci_dma_map_sync_out_data(struct rt_device *dev, + void *data, rt_size_t size, + rt_ubase_t *dma_handle, rt_ubase_t flags) +{ + rt_err_t err; + + if (flags & RT_DMA_F_NOCACHE) + { + err = dma_map_nocoherent_sync_out_data(dev, data, size, dma_handle, flags); + } + else + { + err = dma_map_coherent_sync_out_data(dev, data, size, dma_handle, flags); + } + + if (!err && dma_handle) + { + *dma_handle = pci_addr_cpu2dma(dev, *dma_handle); + } + + return err; +} + +static rt_err_t pci_dma_map_sync_in_data(struct rt_device *dev, + void *out_data, rt_size_t size, + rt_ubase_t dma_handle, rt_ubase_t flags) +{ + dma_handle = pci_addr_dma2cpu(dev, dma_handle); + + if (flags & RT_DMA_F_NOCACHE) + { + return dma_map_nocoherent_sync_in_data(dev, out_data, size, dma_handle, flags); + } + + return dma_map_coherent_sync_in_data(dev, out_data, size, dma_handle, flags); +} + +static const struct rt_dma_map_ops pci_dma_map_ops = +{ + .alloc = pci_dma_map_alloc, + .free = pci_dma_map_free, + .sync_out_data = pci_dma_map_sync_out_data, + .sync_in_data = pci_dma_map_sync_in_data, +}; + +static const struct rt_dma_map_ops *pci_device_dma_ops(struct rt_device *dev) +{ + struct rt_bus *bus = dev->bus; + struct rt_pci_host_bridge *host_bridge; + + if (!bus || rt_strcmp(bus->name, "pci")) + { + return RT_NULL; + } + + host_bridge = pci_device_host_bridge(dev); + + if (!host_bridge || !host_bridge->dma_regions_nr) + { + return RT_NULL; + } + + return &pci_dma_map_ops; +} +#endif /* RT_USING_PCI */ + +#ifdef RT_USING_OFW +const struct rt_dma_map_ops *rt_dma_ofw_device_map_ops(struct rt_device *dev) +{ + if (!dev || !dev->ofw_node) + { + return RT_NULL; + } + + return ofw_device_dma_ops(dev); +} +#endif /* RT_USING_OFW */ + /** * @brief Select DMA operations for a device * * Priority: * 1. Device-specific dma_ops (if already set) - * 2. Device tree memory-region ops (if device has ofw_node) + * 2. Device tree ops (memory-region pools and/or dma-ranges translation) * 3. Coherent or non-coherent fallback based on device property * + * PCI devices with OFW bind dma_ops early in rt_pci_ofw_device_init(); + * other PCI devices fall back to pci_device_dma_ops() here. + * * The result is cached in dev->dma_ops for subsequent calls. * * @param[in] dev Device to query @@ -409,6 +613,15 @@ static const struct rt_dma_map_ops *device_dma_ops(struct rt_device *dev) #ifdef RT_USING_OFW if (dev->ofw_node && (ops = ofw_device_dma_ops(dev))) { + dev->dma_ops = ops; + return ops; + } +#endif + +#ifdef RT_USING_PCI + if ((ops = pci_device_dma_ops(dev))) + { + dev->dma_ops = ops; return ops; } #endif @@ -443,6 +656,15 @@ static rt_ubase_t dma_pool_alloc(struct rt_dma_pool *pool, rt_size_t size) rt_size_t bit, next_bit, end_bit, max_bits; size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); + + if (!size || size > pool->bits) + { + LOG_W("%s: request %u page(s) exceeds pool capacity %u page(s)", + pool->region.name ? pool->region.name : "", + (unsigned)size, (unsigned)pool->bits); + return RT_NULL; + } + max_bits = pool->bits - size; rt_bitmap_for_each_clear_bit(pool->map, bit, max_bits) @@ -549,10 +771,19 @@ static void *dma_alloc(struct rt_device *dev, rt_size_t size, if (*dma_handle && !(flags & RT_DMA_F_NOMAP)) { - if (flags & RT_DMA_F_NOCACHE) + if (pool->flags & RT_DMA_F_NOCACHE) { dma_buffer = rt_ioremap_nocache((void *)*dma_handle, size); } + else if (flags & RT_DMA_F_NOCACHE) + { + /* Honor caller NOCACHE before LINEAR pool shortcut. */ + dma_buffer = rt_ioremap_nocache((void *)*dma_handle, size); + } + else if (pool->flags & RT_DMA_F_LINEAR) + { + dma_buffer = (void *)(*dma_handle - PV_OFFSET); + } else if (flags & RT_DMA_F_WT) { dma_buffer = rt_ioremap_wt((void *)*dma_handle, size); @@ -607,7 +838,10 @@ static void dma_free(struct rt_device *dev, rt_size_t size, if (dma_handle >= pool->region.start && dma_handle <= pool->region.end) { - rt_iounmap(cpu_addr); + if (pool->flags & RT_DMA_F_NOCACHE || !(pool->flags & RT_DMA_F_LINEAR)) + { + rt_iounmap(cpu_addr); + } dma_pool_free(pool, dma_handle, size); @@ -766,12 +1000,48 @@ rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t si return err; } +/** + * @brief Map a linear DMA pool into the kernel address space + * + * Reserved pool memory is excluded from rt_memblock_setup_memory_environment(). + * Install a cached linear mapping so RT_DMA_F_LINEAR pools are CPU-accessible. + */ +static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) +{ + rt_region_t *region = &pool->region; + rt_size_t start = RT_ALIGN_DOWN(region->start, ARCH_PAGE_SIZE); + rt_size_t end = RT_ALIGN(region->end, ARCH_PAGE_SIZE); + void *va; + + if (!(pool->flags & RT_DMA_F_LINEAR) || start >= end) + { + return RT_EOK; + } + + struct rt_mm_va_hint hint = { + .flags = MMF_MAP_FIXED, + .limit_start = rt_kernel_space.start, + .limit_range_size = rt_kernel_space.size, + .map_size = end - start, + .prefer = (void *)(start - PV_OFFSET), + }; + + if (rt_aspace_map_phy(&rt_kernel_space, &hint, MMU_MAP_K_RWCB, + start >> MM_PAGE_SHIFT, &va)) + { + LOG_E("map %s [%p, %p] failed", region->name, start, end); + return -RT_ERROR; + } + + return RT_EOK; +} + /** * @brief Install a DMA memory pool from a region descriptor * * Creates a new DMA pool covering the given memory region. Allocates * a bitmap for page tracking. Pools under 4GB are marked RT_DMA_F_32BITS. - * Pools are automatically marked RT_DMA_F_LINEAR. + * Pools are automatically marked RT_DMA_F_LINEAR and mapped into kernel VA. * * Must be called with the DMA pools lock NOT held. * @@ -824,6 +1094,11 @@ static struct rt_dma_pool *dma_pool_install(rt_region_t *region) rt_list_insert_before(&dma_pool_nodes, &pool->list); region_pool_unlock(); + if (dma_pool_map_linear(pool)) + { + LOG_W("linear map failed for pool %s", region->name); + } + return pool; _fail: diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index 89acc1500902..8fc2dd5b757b 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -346,6 +346,9 @@ void rt_hw_common_setup(void) const char *bootargs; rt_ubase_t dma_pool_base; rt_size_t cma_size = 0, coherent_pool_size = 0; + rt_size_t pool_total; + struct rt_memblock *memory; + struct rt_mmblk_reg *mem_reg; if (!rt_fdt_bootargs_select("cma=", 0, &bootargs)) { @@ -369,9 +372,81 @@ void rt_hw_common_setup(void) coherent_pool_size = 2 * SIZE_MB; } + pool_total = cma_size + coherent_pool_size; + + /* + * Default: place the pool after early boot reservations (kernel/heap/fdt), + * below 4G for RT_DMA_F_32BITS (PCIe). + * + * On a single contiguous RAM bank, keep the pool at the bank tail so + * memblock installs one contiguous free range (avoids an MMU hole). + * The platform must expose RAM through dma_pool_base + pool_total. + */ dma_pool_base = platform_mem_region.end; + + memory = rt_memblock_get_memory(); + { + rt_uint32_t mem_count = 0; + rt_size_t mem_span_start = 0, mem_span_end = 0; + + rt_slist_for_each_entry(mem_reg, &memory->reg_list, node) + { + mem_count++; + if (mem_count == 1) + { + mem_span_start = mem_reg->memreg.start; + } + if (mem_reg->memreg.end > mem_span_end) + { + mem_span_end = mem_reg->memreg.end; + } + } + + if (mem_count == 1 && + dma_pool_base + pool_total <= mem_span_end && + dma_pool_base >= mem_span_start && + dma_pool_base + pool_total < mem_span_end) + { + dma_pool_base = RT_ALIGN_DOWN(mem_span_end - pool_total, ARCH_PAGE_SIZE); + } + } + + if (dma_pool_base + pool_total > (4UL * SIZE_GB)) + { + rt_size_t zone_end = 0; + + rt_slist_for_each_entry(mem_reg, &memory->reg_list, node) + { + rt_size_t start = mem_reg->memreg.start; + rt_size_t end = mem_reg->memreg.end; + + if (start >= (4UL * SIZE_GB)) + { + continue; + } + + if (end > (4UL * SIZE_GB)) + { + end = (4UL * SIZE_GB); + } + + if (end > zone_end) + { + zone_end = end; + } + } + + if (zone_end < platform_mem_region.end + pool_total) + { + LOG_E("No room for sub-4G DMA pool (%u bytes)", pool_total); + break; + } + + dma_pool_base = RT_ALIGN_DOWN(zone_end - pool_total, ARCH_PAGE_SIZE); + } + rt_memblock_reserve_memory("dma-pool", - dma_pool_base, dma_pool_base + cma_size + coherent_pool_size, MEMBLOCK_NONE); + dma_pool_base, dma_pool_base + pool_total, MEMBLOCK_NONE); if (rt_dma_pool_extract(cma_size, coherent_pool_size)) { From ecf60b9a0b531dd3b4121d1e863ddc738e5e1700 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Sat, 1 Aug 2026 22:47:40 +0800 Subject: [PATCH 2/6] [dm][dma] fixup PL330 work flow Fix PL330 channel allocation so device-tree cells select peripheral request lines rather than execution channels. Generate proper peripheral DMA microcode using DMAWFP, DMALDP, DMASTP, and DMAFLUSHP, encode burst lengths correctly, honor transfer direction and non-secure attributes, and allocate microcode from DMA-coherent memory. Signed-off-by: GuEe-GUI <2991707448@qq.com> --- components/drivers/dma/dma-pl330.c | 239 ++++++++++++++++++++++------- 1 file changed, 180 insertions(+), 59 deletions(-) diff --git a/components/drivers/dma/dma-pl330.c b/components/drivers/dma/dma-pl330.c index 8fa207a94d99..0a6bd1fe4e09 100644 --- a/components/drivers/dma/dma-pl330.c +++ b/components/drivers/dma/dma-pl330.c @@ -242,12 +242,14 @@ /** @brief Source address increment flag in CCR */ #define PL330_SRC_INC RT_BIT(0) +#define PL330_SRC_NS RT_BIT(9) /** @brief Source burst size shift in CCR */ #define PL330_SRC_BURST_SIZE_SHIFT 1 /** @brief Source burst length shift in CCR */ #define PL330_SRC_BURST_LEN_SHIFT 4 /** @brief Destination address increment flag in CCR */ #define PL330_DST_INC RT_BIT(14) +#define PL330_DST_NS RT_BIT(23) /** @brief Destination burst size shift in CCR */ #define PL330_DST_BURST_SIZE_SHIFT 15 /** @brief Destination burst length shift in CCR */ @@ -269,20 +271,22 @@ * @brief PL330 DMA channel descriptor * * Extends the generic DMA channel with microcode buffer management. - * The microcode is generated at prep time and stored in microcode_raw - * with alignment padding. + * The microcode is generated at prep time in DMA-coherent memory. */ struct pl330_chan { struct rt_dma_chan parent; /**< Generic DMA channel */ rt_bool_t enabled; /**< Channel is currently in use */ + rt_bool_t is_slave; /**< Channel serves a peripheral request */ + rt_bool_t start_logged; /**< First-start diagnostic emitted */ + rt_bool_t irq_logged; /**< First-IRQ diagnostic emitted */ + rt_uint8_t peri_id; /**< PL330 peripheral request ID */ rt_size_t size; /**< Transfer size for callback reporting */ void *microcode; /**< Aligned microcode buffer pointer */ rt_size_t microcode_len; /**< Microcode length in bytes */ rt_ubase_t microcode_dma; /**< Physical address of microcode buffer */ - rt_uint8_t microcode_raw[PL330_MICROCODE_SIZE + 4]; /**< Raw microcode storage (+4 for alignment) */ }; /** @@ -331,7 +335,7 @@ static void pl330_read_config(struct pl330 *pl330) void *regs = pl330->regs; value = HWREG32(regs + PL330_REG_CR(0)); - pl330->mode_ns = !!PL330_CR0_NUM_EVENTS(value); + pl330->mode_ns = PL330_CR0_MGR_NS_AT_RST(value); pl330->num_chan = PL330_CR0_NUM_CHNLS(value) + 1; pl330->num_events = PL330_CR0_NUM_EVENTS(value) + 1; @@ -358,11 +362,32 @@ static void pl330_read_config(struct pl330 *pl330) * * @return RT_EOK on success, -RT_EINVAL if address width is unsupported */ -static rt_err_t pl330_ccr_config(struct rt_dma_slave_config *conf, rt_uint32_t *ccr) +static rt_err_t pl330_ccr_config(struct rt_dma_slave_config *conf, + rt_bool_t nonsecure, rt_uint32_t *ccr) { - *ccr = PL330_SRC_INC | PL330_DST_INC; - *ccr |= conf->src_maxburst << PL330_SRC_BURST_LEN_SHIFT; - *ccr |= conf->dst_maxburst << PL330_DST_BURST_LEN_SHIFT; + if (!conf->src_maxburst || conf->src_maxburst > 16 || + !conf->dst_maxburst || conf->dst_maxburst > 16) + { + return -RT_EINVAL; + } + + *ccr = (conf->src_maxburst - 1) << PL330_SRC_BURST_LEN_SHIFT; + *ccr |= (conf->dst_maxburst - 1) << PL330_DST_BURST_LEN_SHIFT; + + if (conf->direction != RT_DMA_DEV_TO_MEM) + { + *ccr |= PL330_SRC_INC; + } + + if (conf->direction != RT_DMA_MEM_TO_DEV) + { + *ccr |= PL330_DST_INC; + } + + if (nonsecure) + { + *ccr |= PL330_SRC_NS | PL330_DST_NS; + } switch (conf->src_addr_width) { @@ -512,6 +537,45 @@ static int pl330_cmd_dmast(rt_uint8_t *microcode, rt_uint32_t cond) return PL330_SIZE_DMAST; } +static int pl330_cmd_dmaflushp(rt_uint8_t *microcode, rt_uint8_t peri) +{ + *microcode++ = PL330_CMD_DMAFLUSHP; + *microcode = (peri & 0x1f) << 3; + + return PL330_SIZE_DMAFLUSHP; +} + +static int pl330_cmd_dmaldp(rt_uint8_t *microcode, rt_uint32_t cond, + rt_uint8_t peri) +{ + *microcode++ = PL330_CMD_DMALDP | + (cond == PL330_COND_BURST ? RT_BIT(1) : 0); + *microcode = (peri & 0x1f) << 3; + + return PL330_SIZE_DMALDP; +} + +static int pl330_cmd_dmastp(rt_uint8_t *microcode, rt_uint32_t cond, + rt_uint8_t peri) +{ + *microcode++ = PL330_CMD_DMASTP | + (cond == PL330_COND_BURST ? RT_BIT(1) : 0); + *microcode = (peri & 0x1f) << 3; + + return PL330_SIZE_DMASTP; +} + +static int pl330_cmd_dmawfp(rt_uint8_t *microcode, rt_uint32_t cond, + rt_uint8_t peri) +{ + *microcode++ = PL330_CMD_DMAWFP | + (cond == PL330_COND_BURST ? RT_BIT(1) : 0) | + (cond == PL330_COND_ALWAYS ? RT_BIT(0) : 0); + *microcode = (peri & 0x1f) << 3; + + return PL330_SIZE_DMAWFP; +} + /** * @brief Emit a DMALP (loop begin) microcode instruction * @@ -653,9 +717,8 @@ static rt_uint32_t pl330_chan_id(struct pl330 *pl330, struct pl330_chan *pc) /** * @brief Request a DMA channel from the PL330 controller * - * If fw_data (device tree args) specifies a channel number, that - * specific channel is requested. Otherwise any unallocated channel - * is used. Marks the channel as enabled and unmasks its IRQ. + * Device-tree arguments identify a peripheral request line, while the + * controller allocates any free execution channel. * * @param[in] ctrl DMA controller * @param[in] slave Requesting device @@ -666,46 +729,34 @@ static rt_uint32_t pl330_chan_id(struct pl330 *pl330, struct pl330_chan *pc) static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl, struct rt_device *slave, void *fw_data) { - int idx = -1; + int peri_id = -1; struct pl330_chan *pc; struct pl330 *pl330 = raw_to_pl330(ctrl); struct rt_ofw_cell_args *args = fw_data; - if (args && (idx = args->args[0]) >= pl330->num_chan) + if (args && (peri_id = args->args[0]) >= pl330->num_peri) { return rt_err_ptr(-RT_EINVAL); } - if (idx >= 0) + for (int i = 0; i < pl330->num_chan; ++i) { - pc = &pl330->chans[idx]; + pc = &pl330->chans[i]; - if (pc->enabled) + if (!pc->enabled) { - return rt_err_ptr(-RT_EBUSY); + goto _found; } } - else - { - /* - * Memory to Memory is often called after after DM has been initialized, - * So just return unused chan - */ - for (int i = 0; i < pl330->num_chan; ++i) - { - pc = &pl330->chans[i]; - if (!pc->enabled) - { - goto _found; - } - } - - return RT_NULL; - } + return RT_NULL; _found: pc->enabled = RT_TRUE; + pc->is_slave = peri_id >= 0; + pc->start_logged = RT_FALSE; + pc->irq_logged = RT_FALSE; + pc->peri_id = peri_id >= 0 ? peri_id : 0; HWREG32(pl330->regs + PL330_REG_INTEN) |= RT_BIT(pl330_chan_id(pl330, pc)); return &pc->parent; @@ -723,6 +774,7 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); pc->enabled = RT_FALSE; + pc->is_slave = RT_FALSE; return RT_EOK; } @@ -740,6 +792,7 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) */ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) { + rt_uint32_t id, inst0; struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); struct pl330 *pl330 = raw_to_pl330(chan->ctrl); @@ -750,10 +803,34 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pc->microcode, pc->microcode_len); - HWREG32(pl330->regs + PL330_REG_DBGINST0) = ((pl330_chan_id(pl330, pc) + 1) << 8) | (PL330_CMD_DMAGO << 16); + id = pl330_chan_id(pl330, pc); + inst0 = ((PL330_CMD_DMAGO | (pl330->mode_ns ? RT_BIT(1) : 0)) << 16) | + (id << 24); + + /* DMAGO is issued by the manager thread; its second byte selects a channel. */ + HWREG32(pl330->regs + PL330_REG_DBGINST0) = inst0; HWREG32(pl330->regs + PL330_REG_DBGINST1) = pc->microcode_dma; HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; + if (!pc->start_logged) + { + pc->start_logged = RT_TRUE; + LOG_D("ch%u start peri=%u csr=%x inten=%08x mc=%08x", id, pc->peri_id, + HWREG32(pl330->regs + PL330_REG_CSR(id)) & 0xf, + HWREG32(pl330->regs + PL330_REG_INTEN), + (rt_uint32_t)pc->microcode_dma); + + if ((HWREG32(pl330->regs + PL330_REG_CSR(id)) & 0xf) == PL330_CS_FAULT) + { + LOG_E("ch%u fault ftr=%08x fsrc=%08x fsrd=%08x dsr=%08x cpc=%08x", + id, HWREG32(pl330->regs + PL330_REG_FTR(id)), + HWREG32(pl330->regs + PL330_REG_FSRC), + HWREG32(pl330->regs + PL330_REG_FSRD), + HWREG32(pl330->regs + PL330_REG_DSR), + HWREG32(pl330->regs + PL330_REG_CPC(id))); + } + } + return RT_EOK; } @@ -769,6 +846,7 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) */ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) { + rt_uint32_t id; struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); struct pl330 *pl330 = raw_to_pl330(chan->ctrl); @@ -777,7 +855,11 @@ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) rt_hw_cpu_relax(); } - HWREG32(pl330->regs + PL330_REG_DBGINST0) = ((pl330_chan_id(pl330, pc) + 1) << 8) | PL330_CMD_DMAKILL; + id = pl330_chan_id(pl330, pc); + + /* DMAKILL is executed in the selected channel debug thread. */ + HWREG32(pl330->regs + PL330_REG_DBGINST0) = + (PL330_CMD_DMAKILL << 16) | RT_BIT(0) | (id << 8); HWREG32(pl330->regs + PL330_REG_DBGINST1) = 0; HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; @@ -840,7 +922,7 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, mc = pc->microcode; - if ((err = pl330_ccr_config(conf, &value))) + if ((err = pl330_ccr_config(conf, pl330->mode_ns, &value))) { return err; } @@ -959,7 +1041,7 @@ static rt_err_t pl330_dma_prep_cyclic(struct rt_dma_chan *chan, mc = pc->microcode; - if ((err = pl330_ccr_config(conf, &ccr_val))) + if ((err = pl330_ccr_config(conf, pl330->mode_ns, &ccr_val))) { return err; } @@ -1065,10 +1147,11 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); struct pl330 *pl330 = raw_to_pl330(chan->ctrl); struct rt_dma_slave_config *conf = &chan->conf; + rt_uint32_t cond; mc = pc->microcode; - if ((err = pl330_ccr_config(conf, &ccr_val))) + if ((err = pl330_ccr_config(conf, pl330->mode_ns, &ccr_val))) { return err; } @@ -1086,6 +1169,11 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, mc += pl330_cmd_dmamov(mc, PL330_DIR_DAR, dma_buf_addr); } + if (pc->is_slave && !(pl330->quirk & PL330_QUIRK_BROKEN_NO_FLUSHP)) + { + mc += pl330_cmd_dmaflushp(mc, pc->peri_id); + } + burst_bytes = conf->src_addr_width * conf->src_maxburst; if (!burst_bytes || !buf_len) { @@ -1106,8 +1194,28 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, loop); rt_uint8_t ljmp = mc - pc->microcode; - mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); - mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); + cond = conf->src_maxburst > 1 ? PL330_COND_BURST : PL330_COND_SINGLE; + + if (pc->is_slave) + { + mc += pl330_cmd_dmawfp(mc, cond, pc->peri_id); + + if (dir == RT_DMA_MEM_TO_DEV) + { + mc += pl330_cmd_dmald(mc, cond); + mc += pl330_cmd_dmastp(mc, cond, pc->peri_id); + } + else + { + mc += pl330_cmd_dmaldp(mc, cond, pc->peri_id); + mc += pl330_cmd_dmast(mc, cond); + } + } + else + { + mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); + mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); + } mc += pl330_cmd_dmalpend(mc, PL330_COND_ALWAYS, @@ -1140,11 +1248,8 @@ static const struct rt_dma_controller_ops pl330_dma_ops = { /** * @brief PL330 interrupt service routine * - * Handles all channel interrupts. Reads the Interrupt Status Register - * to identify which channel triggered, then checks the Channel Status - * Register: - * - PL330_CS_CMPLT / PL330_CS_STOP: transfer completed successfully - * - PL330_CS_FAULT / PL330_CS_FLTCMP: transfer faulted + * Handles completion events and reports channel faults. DMASEV can be + * observed before the following DMAEND instruction is executed. * * @param[in] irqno Hardware IRQ number * @param[in] params Controller instance pointer @@ -1170,13 +1275,15 @@ static void pl330_isr(int irqno, void *params) csr = HWREG32(pl330->regs + PL330_REG_CSR(i)) & 0xf; - switch (csr) + if (!pc->irq_logged) { - case PL330_CS_CMPLT: - case PL330_CS_STOP: - rt_dma_chan_done(&pc->parent, pc->size); - break; + pc->irq_logged = RT_TRUE; + LOG_D("ch%d irq mis=%08x csr=%x cpc=%08x", i, isr, csr, + HWREG32(pl330->regs + PL330_REG_CPC(i))); + } + switch (csr) + { case PL330_CS_FAULT: case PL330_CS_FLTCMP: LOG_E("Channel[%d] fault", i); @@ -1184,7 +1291,8 @@ static void pl330_isr(int irqno, void *params) break; default: - LOG_E("Unhandle CSR = %x", csr); + /* DMASEV may be observed before the following DMAEND executes. */ + rt_dma_chan_done(&pc->parent, pc->size); break; } } @@ -1225,6 +1333,17 @@ static void pl330_free(struct pl330 *pl330) if (pl330->chans) { + for (int i = 0; i < pl330->num_chan; ++i) + { + struct pl330_chan *chan = &pl330->chans[i]; + + if (chan->microcode) + { + rt_dma_free_coherent(pl330->parent.dev, PL330_MICROCODE_SIZE, + chan->microcode, chan->microcode_dma); + } + } + rt_free(pl330->chans); } @@ -1262,6 +1381,8 @@ static rt_err_t pl330_probe(struct rt_platform_device *pdev) return -RT_ENOMEM; } + pl330->parent.dev = dev; + pl330->regs = rt_dm_dev_iomap(dev, 0); if (!pl330->regs) @@ -1357,17 +1478,17 @@ static rt_err_t pl330_probe(struct rt_platform_device *pdev) for (int i = 0; i < pl330->num_chan; ++i) { - int offset = 0; struct pl330_chan *chan = &pl330->chans[i]; - chan->microcode_dma = (rt_ubase_t)rt_kmem_v2p(chan->microcode_raw); - offset = RT_ALIGN(chan->microcode_dma, 4) - chan->microcode_dma; - - chan->microcode = chan->microcode_raw + offset; - chan->microcode_dma += offset; + chan->microcode = rt_dma_alloc_coherent(dev, PL330_MICROCODE_SIZE, + &chan->microcode_dma); + if (!chan->microcode) + { + err = -RT_ENOMEM; + goto _fail; + } } - pl330->parent.dev = dev; pl330->parent.ops = &pl330_dma_ops; rt_dma_controller_add_direction(&pl330->parent, RT_DMA_MEM_TO_MEM); rt_dma_controller_add_direction(&pl330->parent, RT_DMA_MEM_TO_DEV); From 7cd04ecd631b0c8582245a7489ebcc606a4aa4c7 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Thu, 6 Aug 2026 23:39:02 +0800 Subject: [PATCH 3/6] style: format code with clang-format --- components/drivers/dma/dma-pl330.c | 80 +++++++++++++++--------------- components/drivers/dma/dma_pool.c | 41 ++++++++------- libcpu/aarch64/common/setup.c | 12 ++--- 3 files changed, 66 insertions(+), 67 deletions(-) diff --git a/components/drivers/dma/dma-pl330.c b/components/drivers/dma/dma-pl330.c index 0a6bd1fe4e09..64191bec4c8f 100644 --- a/components/drivers/dma/dma-pl330.c +++ b/components/drivers/dma/dma-pl330.c @@ -242,14 +242,14 @@ /** @brief Source address increment flag in CCR */ #define PL330_SRC_INC RT_BIT(0) -#define PL330_SRC_NS RT_BIT(9) +#define PL330_SRC_NS RT_BIT(9) /** @brief Source burst size shift in CCR */ #define PL330_SRC_BURST_SIZE_SHIFT 1 /** @brief Source burst length shift in CCR */ #define PL330_SRC_BURST_LEN_SHIFT 4 /** @brief Destination address increment flag in CCR */ #define PL330_DST_INC RT_BIT(14) -#define PL330_DST_NS RT_BIT(23) +#define PL330_DST_NS RT_BIT(23) /** @brief Destination burst size shift in CCR */ #define PL330_DST_BURST_SIZE_SHIFT 15 /** @brief Destination burst length shift in CCR */ @@ -278,9 +278,9 @@ struct pl330_chan struct rt_dma_chan parent; /**< Generic DMA channel */ rt_bool_t enabled; /**< Channel is currently in use */ - rt_bool_t is_slave; /**< Channel serves a peripheral request */ - rt_bool_t start_logged; /**< First-start diagnostic emitted */ - rt_bool_t irq_logged; /**< First-IRQ diagnostic emitted */ + rt_bool_t is_slave; /**< Channel serves a peripheral request */ + rt_bool_t start_logged; /**< First-start diagnostic emitted */ + rt_bool_t irq_logged; /**< First-IRQ diagnostic emitted */ rt_uint8_t peri_id; /**< PL330 peripheral request ID */ rt_size_t size; /**< Transfer size for callback reporting */ @@ -335,7 +335,7 @@ static void pl330_read_config(struct pl330 *pl330) void *regs = pl330->regs; value = HWREG32(regs + PL330_REG_CR(0)); - pl330->mode_ns = PL330_CR0_MGR_NS_AT_RST(value); + pl330->mode_ns = PL330_CR0_MGR_NS_AT_RST(value); pl330->num_chan = PL330_CR0_NUM_CHNLS(value) + 1; pl330->num_events = PL330_CR0_NUM_EVENTS(value) + 1; @@ -363,7 +363,7 @@ static void pl330_read_config(struct pl330 *pl330) * @return RT_EOK on success, -RT_EINVAL if address width is unsupported */ static rt_err_t pl330_ccr_config(struct rt_dma_slave_config *conf, - rt_bool_t nonsecure, rt_uint32_t *ccr) + rt_bool_t nonsecure, rt_uint32_t *ccr) { if (!conf->src_maxburst || conf->src_maxburst > 16 || !conf->dst_maxburst || conf->dst_maxburst > 16) @@ -371,7 +371,7 @@ static rt_err_t pl330_ccr_config(struct rt_dma_slave_config *conf, return -RT_EINVAL; } - *ccr = (conf->src_maxburst - 1) << PL330_SRC_BURST_LEN_SHIFT; + *ccr = (conf->src_maxburst - 1) << PL330_SRC_BURST_LEN_SHIFT; *ccr |= (conf->dst_maxburst - 1) << PL330_DST_BURST_LEN_SHIFT; if (conf->direction != RT_DMA_DEV_TO_MEM) @@ -540,38 +540,38 @@ static int pl330_cmd_dmast(rt_uint8_t *microcode, rt_uint32_t cond) static int pl330_cmd_dmaflushp(rt_uint8_t *microcode, rt_uint8_t peri) { *microcode++ = PL330_CMD_DMAFLUSHP; - *microcode = (peri & 0x1f) << 3; + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMAFLUSHP; } static int pl330_cmd_dmaldp(rt_uint8_t *microcode, rt_uint32_t cond, - rt_uint8_t peri) + rt_uint8_t peri) { *microcode++ = PL330_CMD_DMALDP | - (cond == PL330_COND_BURST ? RT_BIT(1) : 0); - *microcode = (peri & 0x1f) << 3; + (cond == PL330_COND_BURST ? RT_BIT(1) : 0); + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMALDP; } static int pl330_cmd_dmastp(rt_uint8_t *microcode, rt_uint32_t cond, - rt_uint8_t peri) + rt_uint8_t peri) { *microcode++ = PL330_CMD_DMASTP | - (cond == PL330_COND_BURST ? RT_BIT(1) : 0); - *microcode = (peri & 0x1f) << 3; + (cond == PL330_COND_BURST ? RT_BIT(1) : 0); + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMASTP; } static int pl330_cmd_dmawfp(rt_uint8_t *microcode, rt_uint32_t cond, - rt_uint8_t peri) + rt_uint8_t peri) { *microcode++ = PL330_CMD_DMAWFP | - (cond == PL330_COND_BURST ? RT_BIT(1) : 0) | - (cond == PL330_COND_ALWAYS ? RT_BIT(0) : 0); - *microcode = (peri & 0x1f) << 3; + (cond == PL330_COND_BURST ? RT_BIT(1) : 0) | + (cond == PL330_COND_ALWAYS ? RT_BIT(0) : 0); + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMAWFP; } @@ -729,7 +729,7 @@ static rt_uint32_t pl330_chan_id(struct pl330 *pl330, struct pl330_chan *pc) static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl, struct rt_device *slave, void *fw_data) { - int peri_id = -1; + int peri_id = -1; struct pl330_chan *pc; struct pl330 *pl330 = raw_to_pl330(ctrl); struct rt_ofw_cell_args *args = fw_data; @@ -753,10 +753,10 @@ static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl _found: pc->enabled = RT_TRUE; - pc->is_slave = peri_id >= 0; - pc->start_logged = RT_FALSE; - pc->irq_logged = RT_FALSE; - pc->peri_id = peri_id >= 0 ? peri_id : 0; + pc->is_slave = peri_id >= 0; + pc->start_logged = RT_FALSE; + pc->irq_logged = RT_FALSE; + pc->peri_id = peri_id >= 0 ? peri_id : 0; HWREG32(pl330->regs + PL330_REG_INTEN) |= RT_BIT(pl330_chan_id(pl330, pc)); return &pc->parent; @@ -792,7 +792,7 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) */ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) { - rt_uint32_t id, inst0; + rt_uint32_t id, inst0; struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); struct pl330 *pl330 = raw_to_pl330(chan->ctrl); @@ -803,7 +803,7 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pc->microcode, pc->microcode_len); - id = pl330_chan_id(pl330, pc); + id = pl330_chan_id(pl330, pc); inst0 = ((PL330_CMD_DMAGO | (pl330->mode_ns ? RT_BIT(1) : 0)) << 16) | (id << 24); @@ -816,18 +816,18 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) { pc->start_logged = RT_TRUE; LOG_D("ch%u start peri=%u csr=%x inten=%08x mc=%08x", id, pc->peri_id, - HWREG32(pl330->regs + PL330_REG_CSR(id)) & 0xf, - HWREG32(pl330->regs + PL330_REG_INTEN), - (rt_uint32_t)pc->microcode_dma); + HWREG32(pl330->regs + PL330_REG_CSR(id)) & 0xf, + HWREG32(pl330->regs + PL330_REG_INTEN), + (rt_uint32_t)pc->microcode_dma); if ((HWREG32(pl330->regs + PL330_REG_CSR(id)) & 0xf) == PL330_CS_FAULT) { LOG_E("ch%u fault ftr=%08x fsrc=%08x fsrd=%08x dsr=%08x cpc=%08x", - id, HWREG32(pl330->regs + PL330_REG_FTR(id)), - HWREG32(pl330->regs + PL330_REG_FSRC), - HWREG32(pl330->regs + PL330_REG_FSRD), - HWREG32(pl330->regs + PL330_REG_DSR), - HWREG32(pl330->regs + PL330_REG_CPC(id))); + id, HWREG32(pl330->regs + PL330_REG_FTR(id)), + HWREG32(pl330->regs + PL330_REG_FSRC), + HWREG32(pl330->regs + PL330_REG_FSRD), + HWREG32(pl330->regs + PL330_REG_DSR), + HWREG32(pl330->regs + PL330_REG_CPC(id))); } } @@ -846,7 +846,7 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) */ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) { - rt_uint32_t id; + rt_uint32_t id; struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); struct pl330 *pl330 = raw_to_pl330(chan->ctrl); @@ -859,7 +859,7 @@ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) /* DMAKILL is executed in the selected channel debug thread. */ HWREG32(pl330->regs + PL330_REG_DBGINST0) = - (PL330_CMD_DMAKILL << 16) | RT_BIT(0) | (id << 8); + (PL330_CMD_DMAKILL << 16) | RT_BIT(0) | (id << 8); HWREG32(pl330->regs + PL330_REG_DBGINST1) = 0; HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; @@ -1147,7 +1147,7 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); struct pl330 *pl330 = raw_to_pl330(chan->ctrl); struct rt_dma_slave_config *conf = &chan->conf; - rt_uint32_t cond; + rt_uint32_t cond; mc = pc->microcode; @@ -1279,7 +1279,7 @@ static void pl330_isr(int irqno, void *params) { pc->irq_logged = RT_TRUE; LOG_D("ch%d irq mis=%08x csr=%x cpc=%08x", i, isr, csr, - HWREG32(pl330->regs + PL330_REG_CPC(i))); + HWREG32(pl330->regs + PL330_REG_CPC(i))); } switch (csr) @@ -1340,7 +1340,7 @@ static void pl330_free(struct pl330 *pl330) if (chan->microcode) { rt_dma_free_coherent(pl330->parent.dev, PL330_MICROCODE_SIZE, - chan->microcode, chan->microcode_dma); + chan->microcode, chan->microcode_dma); } } @@ -1481,7 +1481,7 @@ static rt_err_t pl330_probe(struct rt_platform_device *pdev) struct pl330_chan *chan = &pl330->chans[i]; chan->microcode = rt_dma_alloc_coherent(dev, PL330_MICROCODE_SIZE, - &chan->microcode_dma); + &chan->microcode_dma); if (!chan->microcode) { err = -RT_ENOMEM; diff --git a/components/drivers/dma/dma_pool.c b/components/drivers/dma/dma_pool.c index 88045b0851d0..ffa64a75d910 100644 --- a/components/drivers/dma/dma_pool.c +++ b/components/drivers/dma/dma_pool.c @@ -206,8 +206,8 @@ static void *ofw_dma_map_alloc(struct rt_device *dev, rt_size_t size, { void *cpu_addr; - flags |= RT_DMA_F_32BITS; - cpu_addr = dma_alloc(dev, size, dma_handle, flags); + flags |= RT_DMA_F_32BITS; + cpu_addr = dma_alloc(dev, size, dma_handle, flags); if (cpu_addr && dma_handle) { @@ -423,7 +423,7 @@ static rt_uint64_t pci_host_cpu_to_bus(struct rt_pci_host_bridge *host_bridge, r struct rt_pci_bus_region *region = &host_bridge->dma_regions[i]; if (cpu_addr >= region->cpu_addr && - cpu_addr < region->cpu_addr + region->size) + cpu_addr < region->cpu_addr + region->size) { return region->phy_addr + (cpu_addr - region->cpu_addr); } @@ -454,7 +454,7 @@ static rt_uint64_t pci_host_bus_to_cpu(struct rt_pci_host_bridge *host_bridge, r static rt_ubase_t pci_addr_cpu2dma(struct rt_device *dev, rt_ubase_t addr) { - rt_uint64_t pci_dma; + rt_uint64_t pci_dma; struct rt_pci_host_bridge *host_bridge = pci_device_host_bridge(dev); if (!host_bridge) @@ -469,7 +469,7 @@ static rt_ubase_t pci_addr_cpu2dma(struct rt_device *dev, rt_ubase_t addr) static rt_ubase_t pci_addr_dma2cpu(struct rt_device *dev, rt_ubase_t addr) { - rt_uint64_t cpu_addr; + rt_uint64_t cpu_addr; struct rt_pci_host_bridge *host_bridge = pci_device_host_bridge(dev); if (!host_bridge) @@ -487,8 +487,8 @@ static void *pci_dma_map_alloc(struct rt_device *dev, rt_size_t size, { void *cpu_addr; - flags |= RT_DMA_F_32BITS; - cpu_addr = dma_alloc(dev, size, dma_handle, flags); + flags |= RT_DMA_F_32BITS; + cpu_addr = dma_alloc(dev, size, dma_handle, flags); if (cpu_addr && dma_handle) { @@ -543,19 +543,18 @@ static rt_err_t pci_dma_map_sync_in_data(struct rt_device *dev, return dma_map_coherent_sync_in_data(dev, out_data, size, dma_handle, flags); } -static const struct rt_dma_map_ops pci_dma_map_ops = -{ - .alloc = pci_dma_map_alloc, - .free = pci_dma_map_free, +static const struct rt_dma_map_ops pci_dma_map_ops = { + .alloc = pci_dma_map_alloc, + .free = pci_dma_map_free, .sync_out_data = pci_dma_map_sync_out_data, - .sync_in_data = pci_dma_map_sync_in_data, + .sync_in_data = pci_dma_map_sync_in_data, }; static const struct rt_dma_map_ops *pci_device_dma_ops(struct rt_device *dev) { - struct rt_bus *bus = dev->bus; + struct rt_bus *bus = dev->bus; struct rt_pci_host_bridge *host_bridge; - + if (!bus || rt_strcmp(bus->name, "pci")) { return RT_NULL; @@ -1009,9 +1008,9 @@ rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t si static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) { rt_region_t *region = &pool->region; - rt_size_t start = RT_ALIGN_DOWN(region->start, ARCH_PAGE_SIZE); - rt_size_t end = RT_ALIGN(region->end, ARCH_PAGE_SIZE); - void *va; + rt_size_t start = RT_ALIGN_DOWN(region->start, ARCH_PAGE_SIZE); + rt_size_t end = RT_ALIGN(region->end, ARCH_PAGE_SIZE); + void *va; if (!(pool->flags & RT_DMA_F_LINEAR) || start >= end) { @@ -1019,11 +1018,11 @@ static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) } struct rt_mm_va_hint hint = { - .flags = MMF_MAP_FIXED, - .limit_start = rt_kernel_space.start, + .flags = MMF_MAP_FIXED, + .limit_start = rt_kernel_space.start, .limit_range_size = rt_kernel_space.size, - .map_size = end - start, - .prefer = (void *)(start - PV_OFFSET), + .map_size = end - start, + .prefer = (void *)(start - PV_OFFSET), }; if (rt_aspace_map_phy(&rt_kernel_space, &hint, MMU_MAP_K_RWCB, diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index 8fc2dd5b757b..69d3d5bfde69 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -346,8 +346,8 @@ void rt_hw_common_setup(void) const char *bootargs; rt_ubase_t dma_pool_base; rt_size_t cma_size = 0, coherent_pool_size = 0; - rt_size_t pool_total; - struct rt_memblock *memory; + rt_size_t pool_total; + struct rt_memblock *memory; struct rt_mmblk_reg *mem_reg; if (!rt_fdt_bootargs_select("cma=", 0, &bootargs)) @@ -386,8 +386,8 @@ void rt_hw_common_setup(void) memory = rt_memblock_get_memory(); { - rt_uint32_t mem_count = 0; - rt_size_t mem_span_start = 0, mem_span_end = 0; + rt_uint32_t mem_count = 0; + rt_size_t mem_span_start = 0, mem_span_end = 0; rt_slist_for_each_entry(mem_reg, &memory->reg_list, node) { @@ -418,7 +418,7 @@ void rt_hw_common_setup(void) rt_slist_for_each_entry(mem_reg, &memory->reg_list, node) { rt_size_t start = mem_reg->memreg.start; - rt_size_t end = mem_reg->memreg.end; + rt_size_t end = mem_reg->memreg.end; if (start >= (4UL * SIZE_GB)) { @@ -446,7 +446,7 @@ void rt_hw_common_setup(void) } rt_memblock_reserve_memory("dma-pool", - dma_pool_base, dma_pool_base + pool_total, MEMBLOCK_NONE); + dma_pool_base, dma_pool_base + pool_total, MEMBLOCK_NONE); if (rt_dma_pool_extract(cma_size, coherent_pool_size)) { From a162aa315d8084832d929e51550176562f1bde98 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Fri, 7 Aug 2026 08:51:32 +0800 Subject: [PATCH 4/6] style: format complete changed files with clang-format --- components/drivers/dma/dma-pl330.c | 200 ++++++++++++++--------------- components/drivers/dma/dma_pool.c | 70 +++++----- libcpu/aarch64/common/setup.c | 93 +++++++------- 3 files changed, 181 insertions(+), 182 deletions(-) diff --git a/components/drivers/dma/dma-pl330.c b/components/drivers/dma/dma-pl330.c index 64191bec4c8f..c12e07d1cef9 100644 --- a/components/drivers/dma/dma-pl330.c +++ b/components/drivers/dma/dma-pl330.c @@ -213,25 +213,25 @@ #define PL330_CMD_DMAWMB 0x13 /** @brief Microcode instruction sizes */ -#define PL330_SIZE_DMAADDH 3 -#define PL330_SIZE_DMAEND 1 +#define PL330_SIZE_DMAADDH 3 +#define PL330_SIZE_DMAEND 1 #define PL330_SIZE_DMAFLUSHP 2 -#define PL330_SIZE_DMALD 1 -#define PL330_SIZE_DMALDP 2 -#define PL330_SIZE_DMALP 2 -#define PL330_SIZE_DMALPEND 2 -#define PL330_SIZE_DMAKILL 1 -#define PL330_SIZE_DMAMOV 6 -#define PL330_SIZE_DMANOP 1 -#define PL330_SIZE_DMARMB 1 -#define PL330_SIZE_DMASEV 2 -#define PL330_SIZE_DMAST 1 -#define PL330_SIZE_DMASTP 2 -#define PL330_SIZE_DMASTZ 1 -#define PL330_SIZE_DMAWFE 2 -#define PL330_SIZE_DMAWFP 2 -#define PL330_SIZE_DMAWMB 1 -#define PL330_SIZE_DMAGO 6 +#define PL330_SIZE_DMALD 1 +#define PL330_SIZE_DMALDP 2 +#define PL330_SIZE_DMALP 2 +#define PL330_SIZE_DMALPEND 2 +#define PL330_SIZE_DMAKILL 1 +#define PL330_SIZE_DMAMOV 6 +#define PL330_SIZE_DMANOP 1 +#define PL330_SIZE_DMARMB 1 +#define PL330_SIZE_DMASEV 2 +#define PL330_SIZE_DMAST 1 +#define PL330_SIZE_DMASTP 2 +#define PL330_SIZE_DMASTZ 1 +#define PL330_SIZE_DMAWFE 2 +#define PL330_SIZE_DMAWFP 2 +#define PL330_SIZE_DMAWMB 1 +#define PL330_SIZE_DMAGO 6 /** @brief DMAMOV to Source Address Register */ #define PL330_DIR_SAR 0 @@ -277,15 +277,15 @@ struct pl330_chan { struct rt_dma_chan parent; /**< Generic DMA channel */ - rt_bool_t enabled; /**< Channel is currently in use */ + rt_bool_t enabled; /**< Channel is currently in use */ rt_bool_t is_slave; /**< Channel serves a peripheral request */ rt_bool_t start_logged; /**< First-start diagnostic emitted */ rt_bool_t irq_logged; /**< First-IRQ diagnostic emitted */ rt_uint8_t peri_id; /**< PL330 peripheral request ID */ - rt_size_t size; /**< Transfer size for callback reporting */ + rt_size_t size; /**< Transfer size for callback reporting */ - void *microcode; /**< Aligned microcode buffer pointer */ - rt_size_t microcode_len; /**< Microcode length in bytes */ + void *microcode; /**< Aligned microcode buffer pointer */ + rt_size_t microcode_len; /**< Microcode length in bytes */ rt_ubase_t microcode_dma; /**< Physical address of microcode buffer */ }; @@ -297,8 +297,8 @@ struct pl330 struct rt_dma_controller parent; /**< Generic DMA controller */ void *regs; /**< MMIO register base */ - int irqs_nr; /**< Number of IRQ lines */ - int irqs[AMBA_NR_IRQS]; /**< IRQ numbers */ + int irqs_nr; /**< Number of IRQ lines */ + int irqs[AMBA_NR_IRQS]; /**< IRQ numbers */ #define PL330_QUIRK_BROKEN_NO_FLUSHP RT_BIT(0) /**< Quirk: broken FLUSHP instruction */ #define PL330_QUIRK_PERIPH_BURST RT_BIT(1) /**< Quirk: peripheral burst support */ @@ -314,7 +314,7 @@ struct pl330 struct pl330_chan *chans; /**< Array of channel descriptors */ - struct rt_clk *pclk; /**< APB peripheral clock */ + struct rt_clk *pclk; /**< APB peripheral clock */ struct rt_reset_control *rstc; /**< DMA reset control */ struct rt_reset_control *rstc_ocp; /**< OCP (Open Core Protocol) reset control */ }; @@ -332,11 +332,11 @@ struct pl330 static void pl330_read_config(struct pl330 *pl330) { rt_uint32_t value; - void *regs = pl330->regs; + void *regs = pl330->regs; - value = HWREG32(regs + PL330_REG_CR(0)); + value = HWREG32(regs + PL330_REG_CR(0)); pl330->mode_ns = PL330_CR0_MGR_NS_AT_RST(value); - pl330->num_chan = PL330_CR0_NUM_CHNLS(value) + 1; + pl330->num_chan = PL330_CR0_NUM_CHNLS(value) + 1; pl330->num_events = PL330_CR0_NUM_EVENTS(value) + 1; if (value & PL330_CR0_PERIPH_REQ_SET) @@ -344,8 +344,8 @@ static void pl330_read_config(struct pl330 *pl330) pl330->num_peri = PL330_CR0_NUM_PERIPH(value) + 1; } - value = HWREG32(regs + PL330_REG_CRD); - pl330->data_width = 8 * (1 << PL330_CRD_DATA_WIDTH(value)); + value = HWREG32(regs + PL330_REG_CRD); + pl330->data_width = 8 * (1 << PL330_CRD_DATA_WIDTH(value)); pl330->data_buffer_dep = PL330_CRD_DATA_BUFFER_DEP(value) + 1; pl330->ins = HWREG32(regs + PL330_REG_CR(3)); @@ -494,7 +494,7 @@ static int pl330_cmd_dmald(rt_uint8_t *microcode, rt_uint32_t cond) LOG_D("DMALD %c", ((char[]){ [PL330_COND_SINGLE] = 'S', - [PL330_COND_BURST] = 'B', + [PL330_COND_BURST] = 'B', [PL330_COND_ALWAYS] = 'A' })[cond]); return PL330_SIZE_DMALD; @@ -531,7 +531,7 @@ static int pl330_cmd_dmast(rt_uint8_t *microcode, rt_uint32_t cond) LOG_D("DMAST %c", ((char[]){ [PL330_COND_SINGLE] = 'S', - [PL330_COND_BURST] = 'B', + [PL330_COND_BURST] = 'B', [PL330_COND_ALWAYS] = 'A' })[cond]); return PL330_SIZE_DMAST; @@ -595,8 +595,8 @@ static int pl330_cmd_dmalp(rt_uint8_t *microcode, rt_uint8_t lc, rt_uint16_t loo * 15 ... 8 7 6 5 4 3 2 1 0 * | iter[7:0] |0 0 1 0 0 0 lc 0 */ - *microcode++ = PL330_CMD_DMALP | ((lc & 1) << 1); - *microcode |= loops - 1; + *microcode++ = PL330_CMD_DMALP | ((lc & 1) << 1); + *microcode |= loops - 1; LOG_D("DMALP %u (lc: %c)", loops - 1, lc ? '1' : '0'); @@ -730,9 +730,9 @@ static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl struct rt_device *slave, void *fw_data) { int peri_id = -1; - struct pl330_chan *pc; - struct pl330 *pl330 = raw_to_pl330(ctrl); - struct rt_ofw_cell_args *args = fw_data; + struct pl330_chan *pc; + struct pl330 *pl330 = raw_to_pl330(ctrl); + struct rt_ofw_cell_args *args = fw_data; if (args && (peri_id = args->args[0]) >= pl330->num_peri) { @@ -752,7 +752,7 @@ static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl return RT_NULL; _found: - pc->enabled = RT_TRUE; + pc->enabled = RT_TRUE; pc->is_slave = peri_id >= 0; pc->start_logged = RT_FALSE; pc->irq_logged = RT_FALSE; @@ -773,7 +773,7 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) { struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - pc->enabled = RT_FALSE; + pc->enabled = RT_FALSE; pc->is_slave = RT_FALSE; return RT_EOK; @@ -793,8 +793,8 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) { rt_uint32_t id, inst0; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); while (HWREG32(pl330->regs + PL330_REG_DBGSTATUS) & PL330_DBGSTATUS_BUSY) { @@ -810,7 +810,7 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) /* DMAGO is issued by the manager thread; its second byte selects a channel. */ HWREG32(pl330->regs + PL330_REG_DBGINST0) = inst0; HWREG32(pl330->regs + PL330_REG_DBGINST1) = pc->microcode_dma; - HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; + HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; if (!pc->start_logged) { @@ -847,8 +847,8 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) { rt_uint32_t id; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); while (HWREG32(pl330->regs + PL330_REG_DBGSTATUS) & PL330_DBGSTATUS_BUSY) { @@ -861,7 +861,7 @@ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) HWREG32(pl330->regs + PL330_REG_DBGINST0) = (PL330_CMD_DMAKILL << 16) | RT_BIT(0) | (id << 8); HWREG32(pl330->regs + PL330_REG_DBGINST1) = 0; - HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; + HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; return RT_EOK; } @@ -877,7 +877,7 @@ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) * * @return RT_EOK */ -static rt_err_t pl330_dma_config(struct rt_dma_chan *chan, +static rt_err_t pl330_dma_config(struct rt_dma_chan *chan, struct rt_dma_slave_config *conf) { return RT_EOK; @@ -910,15 +910,15 @@ static rt_err_t pl330_dma_config(struct rt_dma_chan *chan, static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, rt_ubase_t dma_addr_src, rt_ubase_t dma_addr_dst, rt_size_t len) { - void *mc; - rt_err_t err; - rt_uint32_t value; - rt_size_t burst_bytes; - rt_uint8_t ljmp_inner, ljmp_outer; - rt_uint16_t loop, outer, rem, inner_first; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); - struct rt_dma_slave_config *conf = &chan->conf; + void *mc; + rt_err_t err; + rt_uint32_t value; + rt_size_t burst_bytes; + rt_uint8_t ljmp_inner, ljmp_outer; + rt_uint16_t loop, outer, rem, inner_first; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct rt_dma_slave_config *conf = &chan->conf; mc = pc->microcode; @@ -953,7 +953,7 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, } outer = loop / 256; - rem = loop % 256; + rem = loop % 256; if (outer == 0) { @@ -962,11 +962,11 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, inner_first = (loop < 256) ? loop : 256; - mc += pl330_cmd_dmalp(mc, 1, outer); - ljmp_outer = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 1, outer); + ljmp_outer = mc - pc->microcode; - mc += pl330_cmd_dmalp(mc, 0, inner_first); - ljmp_inner = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0, inner_first); + ljmp_inner = mc - pc->microcode; mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); @@ -978,8 +978,8 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, { rt_uint8_t ljmp_inner2; - mc += pl330_cmd_dmalp(mc, 0, rem); - ljmp_inner2 = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0, rem); + ljmp_inner2 = mc - pc->microcode; mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); @@ -995,7 +995,7 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, mc += pl330_cmd_dmaend(mc); - pc->size = len; + pc->size = len; pc->microcode_len = mc - pc->microcode; return RT_EOK; @@ -1030,14 +1030,14 @@ static rt_err_t pl330_dma_prep_cyclic(struct rt_dma_chan *chan, rt_ubase_t dma_buf_addr, rt_size_t buf_len, rt_size_t period_len, enum rt_dma_transfer_direction dir) { - void *mc; - rt_err_t err; - rt_uint32_t ccr_val; - rt_size_t burst_bytes; - rt_uint16_t period_loop, total_periods; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); - struct rt_dma_slave_config *conf = &chan->conf; + void *mc; + rt_err_t err; + rt_uint32_t ccr_val; + rt_size_t burst_bytes; + rt_uint16_t period_loop, total_periods; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct rt_dma_slave_config *conf = &chan->conf; mc = pc->microcode; @@ -1089,12 +1089,12 @@ static rt_err_t pl330_dma_prep_cyclic(struct rt_dma_chan *chan, } /* Outer Loop */ - mc += pl330_cmd_dmalp(mc, 1 /* LC1 */, 0 /* Infinite loop */); - rt_uint8_t outer_ljmp = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 1 /* LC1 */, 0 /* Infinite loop */); + rt_uint8_t outer_ljmp = mc - pc->microcode; /* Inner Loop */ - mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, period_loop); - rt_uint8_t inner_ljmp = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, period_loop); + rt_uint8_t inner_ljmp = mc - pc->microcode; mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); @@ -1139,14 +1139,14 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, rt_ubase_t dma_buf_addr, rt_size_t buf_len, enum rt_dma_transfer_direction dir) { - void *mc; - rt_err_t err; - rt_uint16_t loop; - rt_uint32_t ccr_val; - rt_size_t burst_bytes; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); - struct rt_dma_slave_config *conf = &chan->conf; + void *mc; + rt_err_t err; + rt_uint16_t loop; + rt_uint32_t ccr_val; + rt_size_t burst_bytes; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct rt_dma_slave_config *conf = &chan->conf; rt_uint32_t cond; mc = pc->microcode; @@ -1191,8 +1191,8 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, return -RT_EINVAL; } - mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, loop); - rt_uint8_t ljmp = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, loop); + rt_uint8_t ljmp = mc - pc->microcode; cond = conf->src_maxburst > 1 ? PL330_COND_BURST : PL330_COND_SINGLE; @@ -1228,7 +1228,7 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, mc += pl330_cmd_dmaend(mc); pc->microcode_len = mc - pc->microcode; - pc->size = buf_len; + pc->size = buf_len; return RT_EOK; } @@ -1237,12 +1237,12 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, static const struct rt_dma_controller_ops pl330_dma_ops = { .request_chan = pl330_dma_request_chan, .release_chan = pl330_dma_release_chan, - .start = pl330_dma_start, - .stop = pl330_dma_stop, - .config = pl330_dma_config, - .prep_memcpy = pl330_dma_prep_memcpy, - .prep_cyclic = pl330_dma_prep_cyclic, - .prep_single = pl330_dma_prep_single, + .start = pl330_dma_start, + .stop = pl330_dma_stop, + .config = pl330_dma_config, + .prep_memcpy = pl330_dma_prep_memcpy, + .prep_cyclic = pl330_dma_prep_cyclic, + .prep_single = pl330_dma_prep_single, }; /** @@ -1256,9 +1256,9 @@ static const struct rt_dma_controller_ops pl330_dma_ops = { */ static void pl330_isr(int irqno, void *params) { - rt_uint32_t isr, csr; + rt_uint32_t isr, csr; struct pl330_chan *pc; - struct pl330 *pl330 = params; + struct pl330 *pl330 = params; isr = HWREG32(pl330->regs + PL330_REG_INTMIS); @@ -1371,10 +1371,10 @@ static void pl330_free(struct pl330 *pl330) */ static rt_err_t pl330_probe(struct rt_platform_device *pdev) { - rt_err_t err; - char isr_name[RT_NAME_MAX]; - struct rt_device *dev = &pdev->parent; - struct pl330 *pl330 = rt_calloc(1, sizeof(*pl330)); + rt_err_t err; + char isr_name[RT_NAME_MAX]; + struct rt_device *dev = &pdev->parent; + struct pl330 *pl330 = rt_calloc(1, sizeof(*pl330)); if (!pl330) { @@ -1553,9 +1553,9 @@ static const struct rt_ofw_node_id pl330_ofw_ids[] = { /** @brief PL330 platform driver descriptor */ static struct rt_platform_driver pl330_driver = { .name = "dma-pl330", - .ids = pl330_ofw_ids, + .ids = pl330_ofw_ids, - .probe = pl330_probe, + .probe = pl330_probe, .remove = pl330_remove, }; diff --git a/components/drivers/dma/dma_pool.c b/components/drivers/dma/dma_pool.c index ffa64a75d910..17a7c7a17114 100644 --- a/components/drivers/dma/dma_pool.c +++ b/components/drivers/dma/dma_pool.c @@ -110,7 +110,7 @@ static rt_err_t dma_map_coherent_sync_in_data(struct rt_device *dev, /** @brief DMA map operations for cache-coherent devices */ static const struct rt_dma_map_ops dma_map_coherent_ops = { .sync_out_data = dma_map_coherent_sync_out_data, - .sync_in_data = dma_map_coherent_sync_in_data, + .sync_in_data = dma_map_coherent_sync_in_data, }; /** @@ -160,7 +160,7 @@ static rt_err_t dma_map_nocoherent_sync_in_data(struct rt_device *dev, /** @brief DMA map operations for non-cache-coherent devices */ static const struct rt_dma_map_ops dma_map_nocoherent_ops = { .sync_out_data = dma_map_nocoherent_sync_out_data, - .sync_in_data = dma_map_nocoherent_sync_in_data, + .sync_in_data = dma_map_nocoherent_sync_in_data, }; #ifdef RT_USING_OFW @@ -301,10 +301,10 @@ static rt_err_t ofw_dma_map_sync_in_data(struct rt_device *dev, /** @brief DMA map operations with device tree address translation */ static const struct rt_dma_map_ops ofw_dma_map_ops = { - .alloc = ofw_dma_map_alloc, - .free = ofw_dma_map_free, + .alloc = ofw_dma_map_alloc, + .free = ofw_dma_map_free, .sync_out_data = ofw_dma_map_sync_out_data, - .sync_in_data = ofw_dma_map_sync_in_data, + .sync_in_data = ofw_dma_map_sync_in_data, }; static rt_bool_t ofw_node_has_dma_ranges(struct rt_ofw_node *np) @@ -341,15 +341,15 @@ static rt_bool_t ofw_node_has_dma_ranges(struct rt_ofw_node *np) */ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) { - rt_err_t err; - int region_nr = 0; - const fdt32_t *cell; - rt_phandle phandle; - rt_region_t region; - struct rt_ofw_prop *prop; - struct rt_dma_pool *dma_pool; + rt_err_t err; + int region_nr = 0; + const fdt32_t *cell; + rt_phandle phandle; + rt_region_t region; + struct rt_ofw_prop *prop; + struct rt_dma_pool *dma_pool; const struct rt_dma_map_ops *ops = RT_NULL; - struct rt_ofw_node *mem_np, *np = dev->ofw_node; + struct rt_ofw_node *mem_np, *np = dev->ofw_node; rt_ofw_foreach_prop_u32(np, "memory-region", prop, cell, phandle) { @@ -370,8 +370,8 @@ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) } region.start = addr; - region.end = addr + size; - region.name = rt_dm_dev_get_name(dev); + region.end = addr + size; + region.name = rt_dm_dev_get_name(dev); rt_ofw_node_put(mem_np); @@ -708,7 +708,7 @@ static void dma_pool_free(struct rt_dma_pool *pool, rt_ubase_t offset, rt_size_t { rt_size_t bit = (offset - pool->start) / ARCH_PAGE_SIZE, end_bit; - size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); + size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); end_bit = bit + size; for (; bit < end_bit; ++bit) @@ -737,7 +737,7 @@ static void dma_pool_free(struct rt_dma_pool *pool, rt_ubase_t offset, rt_size_t static void *dma_alloc(struct rt_device *dev, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - void *dma_buffer = RT_NULL; + void *dma_buffer = RT_NULL; struct rt_dma_pool *pool; region_pool_lock(); @@ -867,8 +867,8 @@ static void dma_free(struct rt_device *dev, rt_size_t size, void *rt_dma_alloc(struct rt_device *dev, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - void *dma_buffer = RT_NULL; - rt_ubase_t dma_handle_s = 0; + void *dma_buffer = RT_NULL; + rt_ubase_t dma_handle_s = 0; const struct rt_dma_map_ops *ops; if (!dev || !size) @@ -948,8 +948,8 @@ void rt_dma_free(struct rt_device *dev, rt_size_t size, rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - rt_err_t err; - rt_ubase_t dma_handle_s = 0; + rt_err_t err; + rt_ubase_t dma_handle_s = 0; const struct rt_dma_map_ops *ops; if (!data || !size) @@ -985,7 +985,7 @@ rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size, rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t size, rt_ubase_t dma_handle, rt_ubase_t flags) { - rt_err_t err; + rt_err_t err; const struct rt_dma_map_ops *ops; if (!out_data || !size) @@ -1050,7 +1050,7 @@ static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) */ static struct rt_dma_pool *dma_pool_install(rt_region_t *region) { - rt_err_t err; + rt_err_t err; struct rt_dma_pool *pool; if (!(pool = rt_calloc(1, sizeof(*pool)))) @@ -1071,7 +1071,7 @@ static struct rt_dma_pool *dma_pool_install(rt_region_t *region) } pool->start = RT_ALIGN(pool->region.start, ARCH_PAGE_SIZE); - pool->bits = (pool->region.end - pool->start) / ARCH_PAGE_SIZE; + pool->bits = (pool->region.end - pool->start) / ARCH_PAGE_SIZE; if (!pool->bits) { @@ -1160,10 +1160,10 @@ struct rt_dma_pool *rt_dma_pool_install(rt_region_t *region) */ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) { - struct rt_dma_pool *pool; + struct rt_dma_pool *pool; struct rt_mmblk_reg *reg, *reg_high; - struct rt_memblock *memblock = rt_memblock_get_reserved(); - rt_region_t *region, *region_high = RT_NULL, cma, coherent_pool; + struct rt_memblock *memblock = rt_memblock_get_reserved(); + rt_region_t *region, *region_high = RT_NULL, cma, coherent_pool; if (!memblock) { @@ -1195,7 +1195,7 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) if ((rt_ssize_t)((4UL * SIZE_GB) - region->start) < cma_size) { region_high = region; - reg_high = reg; + reg_high = reg; continue; } @@ -1206,7 +1206,7 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) if (region_high) { region = region_high; - reg = reg_high; + reg = reg_high; LOG_W("No available DMA zone in 4G"); goto _found; @@ -1218,18 +1218,18 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) if (region->end - region->start != cma_size) { cma.start = region->start; - cma.end = cma.start + cma_size; + cma.end = cma.start + cma_size; } else { rt_memcpy(&cma, region, sizeof(cma)); } - coherent_pool.name = "coherent-pool"; + coherent_pool.name = "coherent-pool"; coherent_pool.start = cma.start; - coherent_pool.end = coherent_pool.start + coherent_pool_size; + coherent_pool.end = coherent_pool.start + coherent_pool_size; - cma.name = "cma"; + cma.name = "cma"; cma.start += coherent_pool_size; if (!(pool = rt_dma_pool_install(&coherent_pool))) @@ -1261,8 +1261,8 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) */ static int list_dma_pool(int argc, char **argv) { - int count = 0; - rt_region_t *region; + int count = 0; + rt_region_t *region; struct rt_dma_pool *pool; rt_kprintf("%-*.s Region\n", RT_NAME_MAX, "Name"); diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index 69d3d5bfde69..1db379ab8ae9 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -32,9 +32,9 @@ extern rt_ubase_t _start, _end; extern void _secondary_cpu_entry(void); extern void rt_hw_builtin_fdt(); extern size_t MMUTable[]; -extern void *system_vectors; +extern void *system_vectors; -static void *fdt_ptr = RT_NULL; +static void *fdt_ptr = RT_NULL; static rt_size_t fdt_size = 0; #ifdef RT_USING_SMP @@ -44,13 +44,11 @@ extern struct cpu_ops_t cpu_spin_table_ops; extern int rt_hw_cpu_id(void); #endif -rt_uint64_t rt_cpu_mpidr_table[] = -{ +rt_uint64_t rt_cpu_mpidr_table[] = { [RT_CPUS_NR] = 0, }; -static struct cpu_ops_t *cpu_ops[] = -{ +static struct cpu_ops_t *cpu_ops[] = { #ifdef RT_USING_SMP &cpu_psci_ops, &cpu_spin_table_ops, @@ -60,14 +58,14 @@ static struct cpu_ops_t *cpu_ops[] = #ifdef ARCH_USING_CPUIDLE struct rt_dvfs_idle *cpu_idle[RT_CPUS_NR] = {}; #endif -static struct rt_ofw_node *cpu_np[RT_CPUS_NR] = { }; +static struct rt_ofw_node *cpu_np[RT_CPUS_NR] = {}; void rt_hw_fdt_install_early(void *fdt) { #ifndef RT_USING_BUILTIN_FDT if (fdt != RT_NULL && !fdt_check_header(fdt)) { - fdt_ptr = fdt; + fdt_ptr = fdt; fdt_size = fdt_totalsize(fdt); } #else @@ -89,8 +87,8 @@ static rt_ubase_t cpu_get_cycles(void) static void cpu_loops_per_tick_init(void) { - rt_ubase_t offset; - volatile rt_ubase_t freq, step, cycles_end1, cycles_end2; + rt_ubase_t offset; + volatile rt_ubase_t freq, step, cycles_end1, cycles_end2; volatile rt_uint32_t cycles_count1 = 0, cycles_count2 = 0; rt_hw_sysreg_read(cntfrq_el0, freq); @@ -100,15 +98,15 @@ static void cpu_loops_per_tick_init(void) while (cpu_get_cycles() < cycles_end1) { - __asm__ volatile ("nop"); - __asm__ volatile ("add %0, %0, #1":"=r"(cycles_count1)); + __asm__ volatile("nop"); + __asm__ volatile("add %0, %0, #1" : "=r"(cycles_count1)); } cycles_end2 = cpu_get_cycles() + step; while (cpu_get_cycles() < cycles_end2) { - __asm__ volatile ("add %0, %0, #1":"=r"(cycles_count2)); + __asm__ volatile("add %0, %0, #1" : "=r"(cycles_count2)); } if ((rt_int32_t)(cycles_count2 - cycles_count1) > 0) @@ -146,7 +144,7 @@ rt_weak void rt_hw_idle_wfi(void) { rt_dvfs_idle_entry(cpuidle); - __asm__ volatile ("wfi"); + __asm__ volatile("wfi"); rt_dvfs_idle_exit(cpuidle); @@ -154,7 +152,7 @@ rt_weak void rt_hw_idle_wfi(void) } #endif /* ARCH_USING_CPUIDLE */ - __asm__ volatile ("wfi"); + __asm__ volatile("wfi"); } static void system_vectors_init(void) @@ -164,8 +162,8 @@ static void system_vectors_init(void) rt_inline void cpu_info_init(void) { - int i = 0; - rt_uint64_t mpidr; + int i = 0; + rt_uint64_t mpidr; struct rt_ofw_node *np; /* get boot cpu info */ @@ -185,7 +183,7 @@ rt_inline void cpu_info_init(void) hwid = mpidr; } - cpu_np[i] = np; + cpu_np[i] = np; rt_cpu_mpidr_table[i] = hwid; for (int idx = 0; idx < RT_ARRAY_SIZE(cpu_ops); ++idx) @@ -218,8 +216,8 @@ rt_inline void cpu_info_init(void) rt_inline rt_size_t string_to_size(const char *string, const char *who) { - char unit; - rt_size_t size; + char unit; + rt_size_t size; const char *cp = string; size = atoi(cp); @@ -253,22 +251,22 @@ rt_inline rt_size_t string_to_size(const char *string, const char *who) void rt_hw_common_setup(void) { - rt_uint64_t initrd_ranges[3]; - rt_size_t kernel_start, kernel_end; - rt_size_t heap_start, heap_end; - rt_size_t init_page_start, init_page_end; - rt_size_t fdt_start, fdt_end; - rt_region_t init_page_region = { 0 }; - rt_region_t platform_mem_region = { 0 }; + rt_uint64_t initrd_ranges[3]; + rt_size_t kernel_start, kernel_end; + rt_size_t heap_start, heap_end; + rt_size_t init_page_start, init_page_end; + rt_size_t fdt_start, fdt_end; + rt_region_t init_page_region = { 0 }; + rt_region_t platform_mem_region = { 0 }; static struct mem_desc platform_mem_desc; - const rt_ubase_t pv_off = PV_OFFSET; + const rt_ubase_t pv_off = PV_OFFSET; system_vectors_init(); #ifdef RT_USING_SMART - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xffffffff00000000, 0x20000000, MMUTable, pv_off); + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xffffffff00000000, 0x20000000, MMUTable, pv_off); #else - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xffffd0000000, 0x20000000, MMUTable, 0); + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xffffd0000000, 0x20000000, MMUTable, 0); #endif kernel_start = RT_ALIGN_DOWN((rt_size_t)rt_kmem_v2p((void *)&_start) - 64, ARCH_PAGE_SIZE); @@ -282,9 +280,9 @@ void rt_hw_common_setup(void) platform_mem_region.start = kernel_start; #ifndef RT_USING_BUILTIN_FDT - platform_mem_region.end = fdt_end; + platform_mem_region.end = fdt_end; #else - platform_mem_region.end = init_page_end; + platform_mem_region.end = init_page_end; (void)fdt_start; (void)fdt_end; #endif @@ -308,14 +306,14 @@ void rt_hw_common_setup(void) rt_memmove((void *)(fdt_start - pv_off), fdt_ptr, fdt_size); fdt_ptr = (void *)fdt_start - pv_off; #else - fdt_ptr = &rt_hw_builtin_fdt; + fdt_ptr = &rt_hw_builtin_fdt; fdt_size = fdt_totalsize(fdt_ptr); #endif /* RT_USING_BUILTIN_FDT */ rt_system_heap_init((void *)(heap_start - pv_off), (void *)(heap_end - pv_off)); init_page_region.start = init_page_start - pv_off; - init_page_region.end = init_page_end - pv_off; + init_page_region.end = init_page_end - pv_off; rt_page_init(init_page_region); /* create MMU mapping of kernel memory */ @@ -324,8 +322,8 @@ void rt_hw_common_setup(void) platform_mem_desc.paddr_start = platform_mem_region.start; platform_mem_desc.vaddr_start = platform_mem_region.start - pv_off; - platform_mem_desc.vaddr_end = platform_mem_region.end - pv_off - 1; - platform_mem_desc.attr = NORMAL_MEM; + platform_mem_desc.vaddr_end = platform_mem_region.end - pv_off - 1; + platform_mem_desc.attr = NORMAL_MEM; rt_hw_mmu_setup(&rt_kernel_space, &platform_mem_desc, 1); @@ -342,10 +340,11 @@ void rt_hw_common_setup(void) rt_fdt_scan_memory(); #ifdef RT_USING_DMA - do { - const char *bootargs; - rt_ubase_t dma_pool_base; - rt_size_t cma_size = 0, coherent_pool_size = 0; + do + { + const char *bootargs; + rt_ubase_t dma_pool_base; + rt_size_t cma_size = 0, coherent_pool_size = 0; rt_size_t pool_total; struct rt_memblock *memory; struct rt_mmblk_reg *mem_reg; @@ -365,10 +364,10 @@ void rt_hw_common_setup(void) if (cma_size || coherent_pool_size) { LOG_W("DMA pool %s=%u > %s=%u", - "CMA", cma_size, "coherent-pool", coherent_pool_size); + "CMA", cma_size, "coherent-pool", coherent_pool_size); } - cma_size = 8 * SIZE_MB; + cma_size = 8 * SIZE_MB; coherent_pool_size = 2 * SIZE_MB; } @@ -451,7 +450,7 @@ void rt_hw_common_setup(void) if (rt_dma_pool_extract(cma_size, coherent_pool_size)) { LOG_E("Alloc DMA pool %s=%u, %s=%u fail", - "CMA", cma_size, "coherent-pool", coherent_pool_size); + "CMA", cma_size, "coherent-pool", coherent_pool_size); } } while (0); #endif /* RT_USING_DMA */ @@ -517,7 +516,7 @@ static int cpuidle_init(void) } cpuidle_dev.ofw_node = cpu_np[i]; - cpuidle = rt_dvfs_idle_get(&cpuidle_dev); + cpuidle = rt_dvfs_idle_get(&cpuidle_dev); if (!rt_is_err(cpuidle)) { @@ -533,8 +532,8 @@ INIT_PREV_EXPORT(cpuidle_init); #ifdef RT_USING_SMP rt_weak void rt_hw_secondary_cpu_up(void) { - int cpu_id = rt_hw_cpu_id(); - rt_uint64_t entry = (rt_uint64_t)rt_kmem_v2p(_secondary_cpu_entry); + int cpu_id = rt_hw_cpu_id(); + rt_uint64_t entry = (rt_uint64_t)rt_kmem_v2p(_secondary_cpu_entry); if (!entry) { @@ -545,7 +544,7 @@ rt_weak void rt_hw_secondary_cpu_up(void) /* Maybe we are no in the first cpu */ for (int i = 0; i < RT_ARRAY_SIZE(cpu_np); ++i) { - int err; + int err; const char *enable_method; if (!cpu_np[i] || i == cpu_id) From 9a26bacc842cb62e809a226ac5021aa5cca601d7 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Thu, 13 Aug 2026 16:06:58 +0800 Subject: [PATCH 5/6] drivers: dma: fix diagnostic format types --- components/drivers/dma/dma_pool.c | 3 ++- libcpu/aarch64/common/setup.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/components/drivers/dma/dma_pool.c b/components/drivers/dma/dma_pool.c index 17a7c7a17114..2d0769cfc829 100644 --- a/components/drivers/dma/dma_pool.c +++ b/components/drivers/dma/dma_pool.c @@ -1028,7 +1028,8 @@ static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) if (rt_aspace_map_phy(&rt_kernel_space, &hint, MMU_MAP_K_RWCB, start >> MM_PAGE_SHIFT, &va)) { - LOG_E("map %s [%p, %p] failed", region->name, start, end); + LOG_E("map %s [0x%lx, 0x%lx] failed", region->name, + (unsigned long)start, (unsigned long)end); return -RT_ERROR; } diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index 1db379ab8ae9..a58f0de29a4b 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -437,7 +437,8 @@ void rt_hw_common_setup(void) if (zone_end < platform_mem_region.end + pool_total) { - LOG_E("No room for sub-4G DMA pool (%u bytes)", pool_total); + LOG_E("No room for sub-4G DMA pool (%lu bytes)", + (unsigned long)pool_total); break; } From 0207137a1411c9595574547896c4836fbc372be9 Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Fri, 14 Aug 2026 11:25:15 +0800 Subject: [PATCH 6/6] style: format DMA changes for current master --- components/drivers/dma/dma-pl330.c | 200 ++++++++++++++--------------- components/drivers/dma/dma_pool.c | 104 +++++++-------- libcpu/aarch64/common/setup.c | 70 +++++----- 3 files changed, 187 insertions(+), 187 deletions(-) diff --git a/components/drivers/dma/dma-pl330.c b/components/drivers/dma/dma-pl330.c index c12e07d1cef9..7a21d0e6e368 100644 --- a/components/drivers/dma/dma-pl330.c +++ b/components/drivers/dma/dma-pl330.c @@ -277,15 +277,15 @@ struct pl330_chan { struct rt_dma_chan parent; /**< Generic DMA channel */ - rt_bool_t enabled; /**< Channel is currently in use */ - rt_bool_t is_slave; /**< Channel serves a peripheral request */ - rt_bool_t start_logged; /**< First-start diagnostic emitted */ - rt_bool_t irq_logged; /**< First-IRQ diagnostic emitted */ + rt_bool_t enabled; /**< Channel is currently in use */ + rt_bool_t is_slave; /**< Channel serves a peripheral request */ + rt_bool_t start_logged; /**< First-start diagnostic emitted */ + rt_bool_t irq_logged; /**< First-IRQ diagnostic emitted */ rt_uint8_t peri_id; /**< PL330 peripheral request ID */ - rt_size_t size; /**< Transfer size for callback reporting */ + rt_size_t size; /**< Transfer size for callback reporting */ - void *microcode; /**< Aligned microcode buffer pointer */ - rt_size_t microcode_len; /**< Microcode length in bytes */ + void *microcode; /**< Aligned microcode buffer pointer */ + rt_size_t microcode_len; /**< Microcode length in bytes */ rt_ubase_t microcode_dma; /**< Physical address of microcode buffer */ }; @@ -297,8 +297,8 @@ struct pl330 struct rt_dma_controller parent; /**< Generic DMA controller */ void *regs; /**< MMIO register base */ - int irqs_nr; /**< Number of IRQ lines */ - int irqs[AMBA_NR_IRQS]; /**< IRQ numbers */ + int irqs_nr; /**< Number of IRQ lines */ + int irqs[AMBA_NR_IRQS]; /**< IRQ numbers */ #define PL330_QUIRK_BROKEN_NO_FLUSHP RT_BIT(0) /**< Quirk: broken FLUSHP instruction */ #define PL330_QUIRK_PERIPH_BURST RT_BIT(1) /**< Quirk: peripheral burst support */ @@ -314,7 +314,7 @@ struct pl330 struct pl330_chan *chans; /**< Array of channel descriptors */ - struct rt_clk *pclk; /**< APB peripheral clock */ + struct rt_clk *pclk; /**< APB peripheral clock */ struct rt_reset_control *rstc; /**< DMA reset control */ struct rt_reset_control *rstc_ocp; /**< OCP (Open Core Protocol) reset control */ }; @@ -332,11 +332,11 @@ struct pl330 static void pl330_read_config(struct pl330 *pl330) { rt_uint32_t value; - void *regs = pl330->regs; + void *regs = pl330->regs; - value = HWREG32(regs + PL330_REG_CR(0)); - pl330->mode_ns = PL330_CR0_MGR_NS_AT_RST(value); - pl330->num_chan = PL330_CR0_NUM_CHNLS(value) + 1; + value = HWREG32(regs + PL330_REG_CR(0)); + pl330->mode_ns = PL330_CR0_MGR_NS_AT_RST(value); + pl330->num_chan = PL330_CR0_NUM_CHNLS(value) + 1; pl330->num_events = PL330_CR0_NUM_EVENTS(value) + 1; if (value & PL330_CR0_PERIPH_REQ_SET) @@ -344,8 +344,8 @@ static void pl330_read_config(struct pl330 *pl330) pl330->num_peri = PL330_CR0_NUM_PERIPH(value) + 1; } - value = HWREG32(regs + PL330_REG_CRD); - pl330->data_width = 8 * (1 << PL330_CRD_DATA_WIDTH(value)); + value = HWREG32(regs + PL330_REG_CRD); + pl330->data_width = 8 * (1 << PL330_CRD_DATA_WIDTH(value)); pl330->data_buffer_dep = PL330_CRD_DATA_BUFFER_DEP(value) + 1; pl330->ins = HWREG32(regs + PL330_REG_CR(3)); @@ -371,7 +371,7 @@ static rt_err_t pl330_ccr_config(struct rt_dma_slave_config *conf, return -RT_EINVAL; } - *ccr = (conf->src_maxburst - 1) << PL330_SRC_BURST_LEN_SHIFT; + *ccr = (conf->src_maxburst - 1) << PL330_SRC_BURST_LEN_SHIFT; *ccr |= (conf->dst_maxburst - 1) << PL330_DST_BURST_LEN_SHIFT; if (conf->direction != RT_DMA_DEV_TO_MEM) @@ -494,7 +494,7 @@ static int pl330_cmd_dmald(rt_uint8_t *microcode, rt_uint32_t cond) LOG_D("DMALD %c", ((char[]){ [PL330_COND_SINGLE] = 'S', - [PL330_COND_BURST] = 'B', + [PL330_COND_BURST] = 'B', [PL330_COND_ALWAYS] = 'A' })[cond]); return PL330_SIZE_DMALD; @@ -531,7 +531,7 @@ static int pl330_cmd_dmast(rt_uint8_t *microcode, rt_uint32_t cond) LOG_D("DMAST %c", ((char[]){ [PL330_COND_SINGLE] = 'S', - [PL330_COND_BURST] = 'B', + [PL330_COND_BURST] = 'B', [PL330_COND_ALWAYS] = 'A' })[cond]); return PL330_SIZE_DMAST; @@ -540,7 +540,7 @@ static int pl330_cmd_dmast(rt_uint8_t *microcode, rt_uint32_t cond) static int pl330_cmd_dmaflushp(rt_uint8_t *microcode, rt_uint8_t peri) { *microcode++ = PL330_CMD_DMAFLUSHP; - *microcode = (peri & 0x1f) << 3; + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMAFLUSHP; } @@ -550,7 +550,7 @@ static int pl330_cmd_dmaldp(rt_uint8_t *microcode, rt_uint32_t cond, { *microcode++ = PL330_CMD_DMALDP | (cond == PL330_COND_BURST ? RT_BIT(1) : 0); - *microcode = (peri & 0x1f) << 3; + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMALDP; } @@ -560,7 +560,7 @@ static int pl330_cmd_dmastp(rt_uint8_t *microcode, rt_uint32_t cond, { *microcode++ = PL330_CMD_DMASTP | (cond == PL330_COND_BURST ? RT_BIT(1) : 0); - *microcode = (peri & 0x1f) << 3; + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMASTP; } @@ -571,7 +571,7 @@ static int pl330_cmd_dmawfp(rt_uint8_t *microcode, rt_uint32_t cond, *microcode++ = PL330_CMD_DMAWFP | (cond == PL330_COND_BURST ? RT_BIT(1) : 0) | (cond == PL330_COND_ALWAYS ? RT_BIT(0) : 0); - *microcode = (peri & 0x1f) << 3; + *microcode = (peri & 0x1f) << 3; return PL330_SIZE_DMAWFP; } @@ -595,8 +595,8 @@ static int pl330_cmd_dmalp(rt_uint8_t *microcode, rt_uint8_t lc, rt_uint16_t loo * 15 ... 8 7 6 5 4 3 2 1 0 * | iter[7:0] |0 0 1 0 0 0 lc 0 */ - *microcode++ = PL330_CMD_DMALP | ((lc & 1) << 1); - *microcode |= loops - 1; + *microcode++ = PL330_CMD_DMALP | ((lc & 1) << 1); + *microcode |= loops - 1; LOG_D("DMALP %u (lc: %c)", loops - 1, lc ? '1' : '0'); @@ -729,10 +729,10 @@ static rt_uint32_t pl330_chan_id(struct pl330 *pl330, struct pl330_chan *pc) static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl, struct rt_device *slave, void *fw_data) { - int peri_id = -1; - struct pl330_chan *pc; - struct pl330 *pl330 = raw_to_pl330(ctrl); - struct rt_ofw_cell_args *args = fw_data; + int peri_id = -1; + struct pl330_chan *pc; + struct pl330 *pl330 = raw_to_pl330(ctrl); + struct rt_ofw_cell_args *args = fw_data; if (args && (peri_id = args->args[0]) >= pl330->num_peri) { @@ -752,11 +752,11 @@ static struct rt_dma_chan *pl330_dma_request_chan(struct rt_dma_controller *ctrl return RT_NULL; _found: - pc->enabled = RT_TRUE; - pc->is_slave = peri_id >= 0; - pc->start_logged = RT_FALSE; - pc->irq_logged = RT_FALSE; - pc->peri_id = peri_id >= 0 ? peri_id : 0; + pc->enabled = RT_TRUE; + pc->is_slave = peri_id >= 0; + pc->start_logged = RT_FALSE; + pc->irq_logged = RT_FALSE; + pc->peri_id = peri_id >= 0 ? peri_id : 0; HWREG32(pl330->regs + PL330_REG_INTEN) |= RT_BIT(pl330_chan_id(pl330, pc)); return &pc->parent; @@ -773,7 +773,7 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) { struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - pc->enabled = RT_FALSE; + pc->enabled = RT_FALSE; pc->is_slave = RT_FALSE; return RT_EOK; @@ -792,9 +792,9 @@ static rt_err_t pl330_dma_release_chan(struct rt_dma_chan *chan) */ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) { - rt_uint32_t id, inst0; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + rt_uint32_t id, inst0; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); while (HWREG32(pl330->regs + PL330_REG_DBGSTATUS) & PL330_DBGSTATUS_BUSY) { @@ -803,14 +803,14 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, pc->microcode, pc->microcode_len); - id = pl330_chan_id(pl330, pc); + id = pl330_chan_id(pl330, pc); inst0 = ((PL330_CMD_DMAGO | (pl330->mode_ns ? RT_BIT(1) : 0)) << 16) | (id << 24); /* DMAGO is issued by the manager thread; its second byte selects a channel. */ HWREG32(pl330->regs + PL330_REG_DBGINST0) = inst0; HWREG32(pl330->regs + PL330_REG_DBGINST1) = pc->microcode_dma; - HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; + HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; if (!pc->start_logged) { @@ -846,9 +846,9 @@ static rt_err_t pl330_dma_start(struct rt_dma_chan *chan) */ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) { - rt_uint32_t id; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + rt_uint32_t id; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); while (HWREG32(pl330->regs + PL330_REG_DBGSTATUS) & PL330_DBGSTATUS_BUSY) { @@ -861,7 +861,7 @@ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) HWREG32(pl330->regs + PL330_REG_DBGINST0) = (PL330_CMD_DMAKILL << 16) | RT_BIT(0) | (id << 8); HWREG32(pl330->regs + PL330_REG_DBGINST1) = 0; - HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; + HWREG32(pl330->regs + PL330_REG_DBGCMD) = 0; return RT_EOK; } @@ -877,7 +877,7 @@ static rt_err_t pl330_dma_stop(struct rt_dma_chan *chan) * * @return RT_EOK */ -static rt_err_t pl330_dma_config(struct rt_dma_chan *chan, +static rt_err_t pl330_dma_config(struct rt_dma_chan *chan, struct rt_dma_slave_config *conf) { return RT_EOK; @@ -910,15 +910,15 @@ static rt_err_t pl330_dma_config(struct rt_dma_chan *chan, static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, rt_ubase_t dma_addr_src, rt_ubase_t dma_addr_dst, rt_size_t len) { - void *mc; - rt_err_t err; - rt_uint32_t value; - rt_size_t burst_bytes; - rt_uint8_t ljmp_inner, ljmp_outer; - rt_uint16_t loop, outer, rem, inner_first; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); - struct rt_dma_slave_config *conf = &chan->conf; + void *mc; + rt_err_t err; + rt_uint32_t value; + rt_size_t burst_bytes; + rt_uint8_t ljmp_inner, ljmp_outer; + rt_uint16_t loop, outer, rem, inner_first; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct rt_dma_slave_config *conf = &chan->conf; mc = pc->microcode; @@ -953,7 +953,7 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, } outer = loop / 256; - rem = loop % 256; + rem = loop % 256; if (outer == 0) { @@ -962,11 +962,11 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, inner_first = (loop < 256) ? loop : 256; - mc += pl330_cmd_dmalp(mc, 1, outer); - ljmp_outer = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 1, outer); + ljmp_outer = mc - pc->microcode; - mc += pl330_cmd_dmalp(mc, 0, inner_first); - ljmp_inner = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0, inner_first); + ljmp_inner = mc - pc->microcode; mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); @@ -978,8 +978,8 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, { rt_uint8_t ljmp_inner2; - mc += pl330_cmd_dmalp(mc, 0, rem); - ljmp_inner2 = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0, rem); + ljmp_inner2 = mc - pc->microcode; mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); @@ -995,7 +995,7 @@ static rt_err_t pl330_dma_prep_memcpy(struct rt_dma_chan *chan, mc += pl330_cmd_dmaend(mc); - pc->size = len; + pc->size = len; pc->microcode_len = mc - pc->microcode; return RT_EOK; @@ -1030,14 +1030,14 @@ static rt_err_t pl330_dma_prep_cyclic(struct rt_dma_chan *chan, rt_ubase_t dma_buf_addr, rt_size_t buf_len, rt_size_t period_len, enum rt_dma_transfer_direction dir) { - void *mc; - rt_err_t err; - rt_uint32_t ccr_val; - rt_size_t burst_bytes; - rt_uint16_t period_loop, total_periods; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); - struct rt_dma_slave_config *conf = &chan->conf; + void *mc; + rt_err_t err; + rt_uint32_t ccr_val; + rt_size_t burst_bytes; + rt_uint16_t period_loop, total_periods; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct rt_dma_slave_config *conf = &chan->conf; mc = pc->microcode; @@ -1089,12 +1089,12 @@ static rt_err_t pl330_dma_prep_cyclic(struct rt_dma_chan *chan, } /* Outer Loop */ - mc += pl330_cmd_dmalp(mc, 1 /* LC1 */, 0 /* Infinite loop */); - rt_uint8_t outer_ljmp = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 1 /* LC1 */, 0 /* Infinite loop */); + rt_uint8_t outer_ljmp = mc - pc->microcode; /* Inner Loop */ - mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, period_loop); - rt_uint8_t inner_ljmp = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, period_loop); + rt_uint8_t inner_ljmp = mc - pc->microcode; mc += pl330_cmd_dmald(mc, PL330_COND_ALWAYS); mc += pl330_cmd_dmast(mc, PL330_COND_ALWAYS); @@ -1139,15 +1139,15 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, rt_ubase_t dma_buf_addr, rt_size_t buf_len, enum rt_dma_transfer_direction dir) { - void *mc; - rt_err_t err; - rt_uint16_t loop; - rt_uint32_t ccr_val; - rt_size_t burst_bytes; - struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); - struct pl330 *pl330 = raw_to_pl330(chan->ctrl); - struct rt_dma_slave_config *conf = &chan->conf; - rt_uint32_t cond; + void *mc; + rt_err_t err; + rt_uint16_t loop; + rt_uint32_t ccr_val; + rt_size_t burst_bytes; + struct pl330_chan *pc = rt_container_of(chan, struct pl330_chan, parent); + struct pl330 *pl330 = raw_to_pl330(chan->ctrl); + struct rt_dma_slave_config *conf = &chan->conf; + rt_uint32_t cond; mc = pc->microcode; @@ -1191,8 +1191,8 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, return -RT_EINVAL; } - mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, loop); - rt_uint8_t ljmp = mc - pc->microcode; + mc += pl330_cmd_dmalp(mc, 0 /* LC0 */, loop); + rt_uint8_t ljmp = mc - pc->microcode; cond = conf->src_maxburst > 1 ? PL330_COND_BURST : PL330_COND_SINGLE; @@ -1228,7 +1228,7 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, mc += pl330_cmd_dmaend(mc); pc->microcode_len = mc - pc->microcode; - pc->size = buf_len; + pc->size = buf_len; return RT_EOK; } @@ -1237,12 +1237,12 @@ static rt_err_t pl330_dma_prep_single(struct rt_dma_chan *chan, static const struct rt_dma_controller_ops pl330_dma_ops = { .request_chan = pl330_dma_request_chan, .release_chan = pl330_dma_release_chan, - .start = pl330_dma_start, - .stop = pl330_dma_stop, - .config = pl330_dma_config, - .prep_memcpy = pl330_dma_prep_memcpy, - .prep_cyclic = pl330_dma_prep_cyclic, - .prep_single = pl330_dma_prep_single, + .start = pl330_dma_start, + .stop = pl330_dma_stop, + .config = pl330_dma_config, + .prep_memcpy = pl330_dma_prep_memcpy, + .prep_cyclic = pl330_dma_prep_cyclic, + .prep_single = pl330_dma_prep_single, }; /** @@ -1256,9 +1256,9 @@ static const struct rt_dma_controller_ops pl330_dma_ops = { */ static void pl330_isr(int irqno, void *params) { - rt_uint32_t isr, csr; + rt_uint32_t isr, csr; struct pl330_chan *pc; - struct pl330 *pl330 = params; + struct pl330 *pl330 = params; isr = HWREG32(pl330->regs + PL330_REG_INTMIS); @@ -1371,10 +1371,10 @@ static void pl330_free(struct pl330 *pl330) */ static rt_err_t pl330_probe(struct rt_platform_device *pdev) { - rt_err_t err; - char isr_name[RT_NAME_MAX]; - struct rt_device *dev = &pdev->parent; - struct pl330 *pl330 = rt_calloc(1, sizeof(*pl330)); + rt_err_t err; + char isr_name[RT_NAME_MAX]; + struct rt_device *dev = &pdev->parent; + struct pl330 *pl330 = rt_calloc(1, sizeof(*pl330)); if (!pl330) { @@ -1553,9 +1553,9 @@ static const struct rt_ofw_node_id pl330_ofw_ids[] = { /** @brief PL330 platform driver descriptor */ static struct rt_platform_driver pl330_driver = { .name = "dma-pl330", - .ids = pl330_ofw_ids, + .ids = pl330_ofw_ids, - .probe = pl330_probe, + .probe = pl330_probe, .remove = pl330_remove, }; diff --git a/components/drivers/dma/dma_pool.c b/components/drivers/dma/dma_pool.c index 2d0769cfc829..75e28cced694 100644 --- a/components/drivers/dma/dma_pool.c +++ b/components/drivers/dma/dma_pool.c @@ -110,7 +110,7 @@ static rt_err_t dma_map_coherent_sync_in_data(struct rt_device *dev, /** @brief DMA map operations for cache-coherent devices */ static const struct rt_dma_map_ops dma_map_coherent_ops = { .sync_out_data = dma_map_coherent_sync_out_data, - .sync_in_data = dma_map_coherent_sync_in_data, + .sync_in_data = dma_map_coherent_sync_in_data, }; /** @@ -160,7 +160,7 @@ static rt_err_t dma_map_nocoherent_sync_in_data(struct rt_device *dev, /** @brief DMA map operations for non-cache-coherent devices */ static const struct rt_dma_map_ops dma_map_nocoherent_ops = { .sync_out_data = dma_map_nocoherent_sync_out_data, - .sync_in_data = dma_map_nocoherent_sync_in_data, + .sync_in_data = dma_map_nocoherent_sync_in_data, }; #ifdef RT_USING_OFW @@ -206,8 +206,8 @@ static void *ofw_dma_map_alloc(struct rt_device *dev, rt_size_t size, { void *cpu_addr; - flags |= RT_DMA_F_32BITS; - cpu_addr = dma_alloc(dev, size, dma_handle, flags); + flags |= RT_DMA_F_32BITS; + cpu_addr = dma_alloc(dev, size, dma_handle, flags); if (cpu_addr && dma_handle) { @@ -301,10 +301,10 @@ static rt_err_t ofw_dma_map_sync_in_data(struct rt_device *dev, /** @brief DMA map operations with device tree address translation */ static const struct rt_dma_map_ops ofw_dma_map_ops = { - .alloc = ofw_dma_map_alloc, - .free = ofw_dma_map_free, + .alloc = ofw_dma_map_alloc, + .free = ofw_dma_map_free, .sync_out_data = ofw_dma_map_sync_out_data, - .sync_in_data = ofw_dma_map_sync_in_data, + .sync_in_data = ofw_dma_map_sync_in_data, }; static rt_bool_t ofw_node_has_dma_ranges(struct rt_ofw_node *np) @@ -341,15 +341,15 @@ static rt_bool_t ofw_node_has_dma_ranges(struct rt_ofw_node *np) */ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) { - rt_err_t err; - int region_nr = 0; - const fdt32_t *cell; - rt_phandle phandle; - rt_region_t region; - struct rt_ofw_prop *prop; - struct rt_dma_pool *dma_pool; + rt_err_t err; + int region_nr = 0; + const fdt32_t *cell; + rt_phandle phandle; + rt_region_t region; + struct rt_ofw_prop *prop; + struct rt_dma_pool *dma_pool; const struct rt_dma_map_ops *ops = RT_NULL; - struct rt_ofw_node *mem_np, *np = dev->ofw_node; + struct rt_ofw_node *mem_np, *np = dev->ofw_node; rt_ofw_foreach_prop_u32(np, "memory-region", prop, cell, phandle) { @@ -370,8 +370,8 @@ static const struct rt_dma_map_ops *ofw_device_dma_ops(struct rt_device *dev) } region.start = addr; - region.end = addr + size; - region.name = rt_dm_dev_get_name(dev); + region.end = addr + size; + region.name = rt_dm_dev_get_name(dev); rt_ofw_node_put(mem_np); @@ -454,7 +454,7 @@ static rt_uint64_t pci_host_bus_to_cpu(struct rt_pci_host_bridge *host_bridge, r static rt_ubase_t pci_addr_cpu2dma(struct rt_device *dev, rt_ubase_t addr) { - rt_uint64_t pci_dma; + rt_uint64_t pci_dma; struct rt_pci_host_bridge *host_bridge = pci_device_host_bridge(dev); if (!host_bridge) @@ -469,7 +469,7 @@ static rt_ubase_t pci_addr_cpu2dma(struct rt_device *dev, rt_ubase_t addr) static rt_ubase_t pci_addr_dma2cpu(struct rt_device *dev, rt_ubase_t addr) { - rt_uint64_t cpu_addr; + rt_uint64_t cpu_addr; struct rt_pci_host_bridge *host_bridge = pci_device_host_bridge(dev); if (!host_bridge) @@ -487,8 +487,8 @@ static void *pci_dma_map_alloc(struct rt_device *dev, rt_size_t size, { void *cpu_addr; - flags |= RT_DMA_F_32BITS; - cpu_addr = dma_alloc(dev, size, dma_handle, flags); + flags |= RT_DMA_F_32BITS; + cpu_addr = dma_alloc(dev, size, dma_handle, flags); if (cpu_addr && dma_handle) { @@ -544,15 +544,15 @@ static rt_err_t pci_dma_map_sync_in_data(struct rt_device *dev, } static const struct rt_dma_map_ops pci_dma_map_ops = { - .alloc = pci_dma_map_alloc, - .free = pci_dma_map_free, + .alloc = pci_dma_map_alloc, + .free = pci_dma_map_free, .sync_out_data = pci_dma_map_sync_out_data, - .sync_in_data = pci_dma_map_sync_in_data, + .sync_in_data = pci_dma_map_sync_in_data, }; static const struct rt_dma_map_ops *pci_device_dma_ops(struct rt_device *dev) { - struct rt_bus *bus = dev->bus; + struct rt_bus *bus = dev->bus; struct rt_pci_host_bridge *host_bridge; if (!bus || rt_strcmp(bus->name, "pci")) @@ -708,7 +708,7 @@ static void dma_pool_free(struct rt_dma_pool *pool, rt_ubase_t offset, rt_size_t { rt_size_t bit = (offset - pool->start) / ARCH_PAGE_SIZE, end_bit; - size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); + size = RT_DIV_ROUND_UP(size, ARCH_PAGE_SIZE); end_bit = bit + size; for (; bit < end_bit; ++bit) @@ -737,7 +737,7 @@ static void dma_pool_free(struct rt_dma_pool *pool, rt_ubase_t offset, rt_size_t static void *dma_alloc(struct rt_device *dev, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - void *dma_buffer = RT_NULL; + void *dma_buffer = RT_NULL; struct rt_dma_pool *pool; region_pool_lock(); @@ -867,8 +867,8 @@ static void dma_free(struct rt_device *dev, rt_size_t size, void *rt_dma_alloc(struct rt_device *dev, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - void *dma_buffer = RT_NULL; - rt_ubase_t dma_handle_s = 0; + void *dma_buffer = RT_NULL; + rt_ubase_t dma_handle_s = 0; const struct rt_dma_map_ops *ops; if (!dev || !size) @@ -948,8 +948,8 @@ void rt_dma_free(struct rt_device *dev, rt_size_t size, rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size, rt_ubase_t *dma_handle, rt_ubase_t flags) { - rt_err_t err; - rt_ubase_t dma_handle_s = 0; + rt_err_t err; + rt_ubase_t dma_handle_s = 0; const struct rt_dma_map_ops *ops; if (!data || !size) @@ -985,7 +985,7 @@ rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size, rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t size, rt_ubase_t dma_handle, rt_ubase_t flags) { - rt_err_t err; + rt_err_t err; const struct rt_dma_map_ops *ops; if (!out_data || !size) @@ -1008,9 +1008,9 @@ rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t si static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) { rt_region_t *region = &pool->region; - rt_size_t start = RT_ALIGN_DOWN(region->start, ARCH_PAGE_SIZE); - rt_size_t end = RT_ALIGN(region->end, ARCH_PAGE_SIZE); - void *va; + rt_size_t start = RT_ALIGN_DOWN(region->start, ARCH_PAGE_SIZE); + rt_size_t end = RT_ALIGN(region->end, ARCH_PAGE_SIZE); + void *va; if (!(pool->flags & RT_DMA_F_LINEAR) || start >= end) { @@ -1018,11 +1018,11 @@ static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) } struct rt_mm_va_hint hint = { - .flags = MMF_MAP_FIXED, - .limit_start = rt_kernel_space.start, + .flags = MMF_MAP_FIXED, + .limit_start = rt_kernel_space.start, .limit_range_size = rt_kernel_space.size, - .map_size = end - start, - .prefer = (void *)(start - PV_OFFSET), + .map_size = end - start, + .prefer = (void *)(start - PV_OFFSET), }; if (rt_aspace_map_phy(&rt_kernel_space, &hint, MMU_MAP_K_RWCB, @@ -1051,7 +1051,7 @@ static rt_err_t dma_pool_map_linear(struct rt_dma_pool *pool) */ static struct rt_dma_pool *dma_pool_install(rt_region_t *region) { - rt_err_t err; + rt_err_t err; struct rt_dma_pool *pool; if (!(pool = rt_calloc(1, sizeof(*pool)))) @@ -1072,7 +1072,7 @@ static struct rt_dma_pool *dma_pool_install(rt_region_t *region) } pool->start = RT_ALIGN(pool->region.start, ARCH_PAGE_SIZE); - pool->bits = (pool->region.end - pool->start) / ARCH_PAGE_SIZE; + pool->bits = (pool->region.end - pool->start) / ARCH_PAGE_SIZE; if (!pool->bits) { @@ -1161,10 +1161,10 @@ struct rt_dma_pool *rt_dma_pool_install(rt_region_t *region) */ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) { - struct rt_dma_pool *pool; + struct rt_dma_pool *pool; struct rt_mmblk_reg *reg, *reg_high; - struct rt_memblock *memblock = rt_memblock_get_reserved(); - rt_region_t *region, *region_high = RT_NULL, cma, coherent_pool; + struct rt_memblock *memblock = rt_memblock_get_reserved(); + rt_region_t *region, *region_high = RT_NULL, cma, coherent_pool; if (!memblock) { @@ -1196,7 +1196,7 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) if ((rt_ssize_t)((4UL * SIZE_GB) - region->start) < cma_size) { region_high = region; - reg_high = reg; + reg_high = reg; continue; } @@ -1207,7 +1207,7 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) if (region_high) { region = region_high; - reg = reg_high; + reg = reg_high; LOG_W("No available DMA zone in 4G"); goto _found; @@ -1219,18 +1219,18 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) if (region->end - region->start != cma_size) { cma.start = region->start; - cma.end = cma.start + cma_size; + cma.end = cma.start + cma_size; } else { rt_memcpy(&cma, region, sizeof(cma)); } - coherent_pool.name = "coherent-pool"; + coherent_pool.name = "coherent-pool"; coherent_pool.start = cma.start; - coherent_pool.end = coherent_pool.start + coherent_pool_size; + coherent_pool.end = coherent_pool.start + coherent_pool_size; - cma.name = "cma"; + cma.name = "cma"; cma.start += coherent_pool_size; if (!(pool = rt_dma_pool_install(&coherent_pool))) @@ -1262,8 +1262,8 @@ rt_err_t rt_dma_pool_extract(rt_size_t cma_size, rt_size_t coherent_pool_size) */ static int list_dma_pool(int argc, char **argv) { - int count = 0; - rt_region_t *region; + int count = 0; + rt_region_t *region; struct rt_dma_pool *pool; rt_kprintf("%-*.s Region\n", RT_NAME_MAX, "Name"); diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index a58f0de29a4b..f91f4e250e97 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -32,9 +32,9 @@ extern rt_ubase_t _start, _end; extern void _secondary_cpu_entry(void); extern void rt_hw_builtin_fdt(); extern size_t MMUTable[]; -extern void *system_vectors; +extern void *system_vectors; -static void *fdt_ptr = RT_NULL; +static void *fdt_ptr = RT_NULL; static rt_size_t fdt_size = 0; #ifdef RT_USING_SMP @@ -65,7 +65,7 @@ void rt_hw_fdt_install_early(void *fdt) #ifndef RT_USING_BUILTIN_FDT if (fdt != RT_NULL && !fdt_check_header(fdt)) { - fdt_ptr = fdt; + fdt_ptr = fdt; fdt_size = fdt_totalsize(fdt); } #else @@ -87,8 +87,8 @@ static rt_ubase_t cpu_get_cycles(void) static void cpu_loops_per_tick_init(void) { - rt_ubase_t offset; - volatile rt_ubase_t freq, step, cycles_end1, cycles_end2; + rt_ubase_t offset; + volatile rt_ubase_t freq, step, cycles_end1, cycles_end2; volatile rt_uint32_t cycles_count1 = 0, cycles_count2 = 0; rt_hw_sysreg_read(cntfrq_el0, freq); @@ -162,8 +162,8 @@ static void system_vectors_init(void) rt_inline void cpu_info_init(void) { - int i = 0; - rt_uint64_t mpidr; + int i = 0; + rt_uint64_t mpidr; struct rt_ofw_node *np; /* get boot cpu info */ @@ -183,7 +183,7 @@ rt_inline void cpu_info_init(void) hwid = mpidr; } - cpu_np[i] = np; + cpu_np[i] = np; rt_cpu_mpidr_table[i] = hwid; for (int idx = 0; idx < RT_ARRAY_SIZE(cpu_ops); ++idx) @@ -216,8 +216,8 @@ rt_inline void cpu_info_init(void) rt_inline rt_size_t string_to_size(const char *string, const char *who) { - char unit; - rt_size_t size; + char unit; + rt_size_t size; const char *cp = string; size = atoi(cp); @@ -251,15 +251,15 @@ rt_inline rt_size_t string_to_size(const char *string, const char *who) void rt_hw_common_setup(void) { - rt_uint64_t initrd_ranges[3]; - rt_size_t kernel_start, kernel_end; - rt_size_t heap_start, heap_end; - rt_size_t init_page_start, init_page_end; - rt_size_t fdt_start, fdt_end; - rt_region_t init_page_region = { 0 }; - rt_region_t platform_mem_region = { 0 }; + rt_uint64_t initrd_ranges[3]; + rt_size_t kernel_start, kernel_end; + rt_size_t heap_start, heap_end; + rt_size_t init_page_start, init_page_end; + rt_size_t fdt_start, fdt_end; + rt_region_t init_page_region = { 0 }; + rt_region_t platform_mem_region = { 0 }; static struct mem_desc platform_mem_desc; - const rt_ubase_t pv_off = PV_OFFSET; + const rt_ubase_t pv_off = PV_OFFSET; system_vectors_init(); @@ -306,14 +306,14 @@ void rt_hw_common_setup(void) rt_memmove((void *)(fdt_start - pv_off), fdt_ptr, fdt_size); fdt_ptr = (void *)fdt_start - pv_off; #else - fdt_ptr = &rt_hw_builtin_fdt; + fdt_ptr = &rt_hw_builtin_fdt; fdt_size = fdt_totalsize(fdt_ptr); #endif /* RT_USING_BUILTIN_FDT */ rt_system_heap_init((void *)(heap_start - pv_off), (void *)(heap_end - pv_off)); init_page_region.start = init_page_start - pv_off; - init_page_region.end = init_page_end - pv_off; + init_page_region.end = init_page_end - pv_off; rt_page_init(init_page_region); /* create MMU mapping of kernel memory */ @@ -322,8 +322,8 @@ void rt_hw_common_setup(void) platform_mem_desc.paddr_start = platform_mem_region.start; platform_mem_desc.vaddr_start = platform_mem_region.start - pv_off; - platform_mem_desc.vaddr_end = platform_mem_region.end - pv_off - 1; - platform_mem_desc.attr = NORMAL_MEM; + platform_mem_desc.vaddr_end = platform_mem_region.end - pv_off - 1; + platform_mem_desc.attr = NORMAL_MEM; rt_hw_mmu_setup(&rt_kernel_space, &platform_mem_desc, 1); @@ -342,11 +342,11 @@ void rt_hw_common_setup(void) #ifdef RT_USING_DMA do { - const char *bootargs; - rt_ubase_t dma_pool_base; - rt_size_t cma_size = 0, coherent_pool_size = 0; - rt_size_t pool_total; - struct rt_memblock *memory; + const char *bootargs; + rt_ubase_t dma_pool_base; + rt_size_t cma_size = 0, coherent_pool_size = 0; + rt_size_t pool_total; + struct rt_memblock *memory; struct rt_mmblk_reg *mem_reg; if (!rt_fdt_bootargs_select("cma=", 0, &bootargs)) @@ -367,7 +367,7 @@ void rt_hw_common_setup(void) "CMA", cma_size, "coherent-pool", coherent_pool_size); } - cma_size = 8 * SIZE_MB; + cma_size = 8 * SIZE_MB; coherent_pool_size = 2 * SIZE_MB; } @@ -385,8 +385,8 @@ void rt_hw_common_setup(void) memory = rt_memblock_get_memory(); { - rt_uint32_t mem_count = 0; - rt_size_t mem_span_start = 0, mem_span_end = 0; + rt_uint32_t mem_count = 0; + rt_size_t mem_span_start = 0, mem_span_end = 0; rt_slist_for_each_entry(mem_reg, &memory->reg_list, node) { @@ -417,7 +417,7 @@ void rt_hw_common_setup(void) rt_slist_for_each_entry(mem_reg, &memory->reg_list, node) { rt_size_t start = mem_reg->memreg.start; - rt_size_t end = mem_reg->memreg.end; + rt_size_t end = mem_reg->memreg.end; if (start >= (4UL * SIZE_GB)) { @@ -517,7 +517,7 @@ static int cpuidle_init(void) } cpuidle_dev.ofw_node = cpu_np[i]; - cpuidle = rt_dvfs_idle_get(&cpuidle_dev); + cpuidle = rt_dvfs_idle_get(&cpuidle_dev); if (!rt_is_err(cpuidle)) { @@ -533,8 +533,8 @@ INIT_PREV_EXPORT(cpuidle_init); #ifdef RT_USING_SMP rt_weak void rt_hw_secondary_cpu_up(void) { - int cpu_id = rt_hw_cpu_id(); - rt_uint64_t entry = (rt_uint64_t)rt_kmem_v2p(_secondary_cpu_entry); + int cpu_id = rt_hw_cpu_id(); + rt_uint64_t entry = (rt_uint64_t)rt_kmem_v2p(_secondary_cpu_entry); if (!entry) { @@ -545,7 +545,7 @@ rt_weak void rt_hw_secondary_cpu_up(void) /* Maybe we are no in the first cpu */ for (int i = 0; i < RT_ARRAY_SIZE(cpu_np); ++i) { - int err; + int err; const char *enable_method; if (!cpu_np[i] || i == cpu_id)