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rcitachrcitach
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fix ra6w1 device bug
1 parent 991f0ff commit 9a8e2fd

6 files changed

Lines changed: 121 additions & 17 deletions

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‎bsp/renesas/libraries/HAL_Drivers/drivers/drv_adc.c‎

Lines changed: 27 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@
2020
#endif /* DRV_DEBUG */
2121
#include <rtdbg.h>
2222

23+
#define R_ADC_REFERENCE_VOLTAGE 0
24+
2325
#if defined(SOC_SERIES_R7KA8P1)
2426

2527
#define R_ADC_Open R_ADC_B_Open
@@ -39,7 +41,8 @@
3941
#define R_ADC_Read R_ADC_W_Read
4042
#define R_ADC_ScanStop R_ADC_W_ScanStop
4143
#define R_ADC_Close R_ADC_W_Close
42-
44+
#undef R_ADC_REFERENCE_VOLTAGE
45+
#define R_ADC_REFERENCE_VOLTAGE R_ADC_W_REFERENCE_VOLTAGE
4346
#endif
4447

4548
struct ra_adc_map ra_adc[] = {
@@ -113,18 +116,37 @@ static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_int8_t channel
113116
LOG_E("get adc value failed.\n");
114117
return -RT_ERROR;
115118
}
119+
#if defined(SOC_SERIES_R7SA6W1)
120+
/* R_ADC_W returns the 12-bit result left-aligned in a 16-bit FIFO field. */
121+
*value >>= 4U;
122+
#endif
116123
return RT_EOK;
117124
}
118125

119126
static rt_uint8_t ra_adc_get_resolution(struct rt_adc_device *device)
120127
{
121-
LOG_W("ra_adc_get_resolution is not supported.");
122-
return 0;
128+
struct ra_adc_map *adc;
129+
130+
RT_ASSERT(device != RT_NULL);
131+
adc = (struct ra_adc_map *)device->parent.user_data;
132+
133+
switch (adc->g_cfg->resolution)
134+
{
135+
case ADC_RESOLUTION_12_BIT:
136+
return 12;
137+
case ADC_RESOLUTION_10_BIT:
138+
return 10;
139+
case ADC_RESOLUTION_7_BIT:
140+
return 7;
141+
case ADC_RESOLUTION_4_BIT:
142+
return 4;
143+
default:
144+
return 0;
145+
}
123146
}
124147
static rt_int16_t ra_adc_get_vref(struct rt_adc_device *device)
125148
{
126-
LOG_W("ra_adc_get_vref is not supported.");
127-
return 0;
149+
return R_ADC_REFERENCE_VOLTAGE;
128150
}
129151

130152
static const struct rt_adc_ops ra_adc_ops = {

‎bsp/renesas/ra6w1-ek/board/Kconfig‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,19 @@ menu "Hardware Drivers Config"
179179
bool "Enable I2C0 bus"
180180
default n
181181
if BSP_USING_HW_I2C0
182+
choice BSP_USING_HW_I2C0_SPEED
183+
prompt "I2C0 Baud Rate Settings"
184+
default BSP_I2C0_RATE_FAST
185+
config BSP_I2C0_RATE_STANDARD
186+
bool "I2C_MASTER_RATE_STANDARD (100 kHz)"
187+
config BSP_I2C0_RATE_FAST
188+
bool "I2C_MASTER_RATE_FAST (400 kHz)"
189+
config BSP_I2C0_RATE_FASTPLUS
190+
bool "I2C_MASTER_RATE_FASTPLUS (1 MHz)"
191+
config BSP_I2C0_RATE_HIGHSPEED
192+
bool "I2C_MASTER_RATE_HIGHSPEED (3.4 MHz)"
193+
endchoice
194+
182195
config BSP_I2C0_SCL_PIN
183196
string "I2C0 SCL pin"
184197
default "p004"
@@ -192,6 +205,20 @@ menu "Hardware Drivers Config"
192205
bool "Enable I2C1 bus"
193206
default n
194207
if BSP_USING_HW_I2C1
208+
209+
choice BSP_USING_HW_I2C1_SPEED
210+
prompt "I2C1 Baud Rate Settings"
211+
default BSP_I2C1_RATE_FAST
212+
config BSP_I2C1_RATE_STANDARD
213+
bool "I2C_MASTER_RATE_STANDARD (100 kHz)"
214+
config BSP_I2C1_RATE_FAST
215+
bool "I2C_MASTER_RATE_FAST (400 kHz)"
216+
config BSP_I2C1_RATE_FASTPLUS
217+
bool "I2C_MASTER_RATE_FASTPLUS (1 MHz)"
218+
config BSP_I2C1_RATE_HIGHSPEED
219+
bool "I2C_MASTER_RATE_HIGHSPEED (3.4 MHz)"
220+
endchoice
221+
195222
config BSP_I2C1_SCL_PIN
196223
string "I2C1 SCL pin"
197224
default "p006"
@@ -208,6 +235,10 @@ menu "Hardware Drivers Config"
208235
select RT_USING_ADC
209236
default n
210237
if BSP_USING_ADC
238+
config R_ADC_W_REFERENCE_VOLTAGE
239+
int "ADC full-scale input voltage (mV)"
240+
default 1400
241+
211242
config BSP_USING_ADC_PIN_NUM
212243
int "ADC channel count"
213244
range 1 4

‎bsp/renesas/ra6w1-ek/board/ports/drv_pwm_w.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
#include "drv_config.h"
88
#include "hal_data.h"
99

10-
#if defined(BSP_USING_PWM) && \
10+
#if defined(BSP_USING_PWM_W) && \
1111
(defined(BSP_USING_PWM0) || defined(BSP_USING_PWM1) || \
1212
defined(BSP_USING_PWM2) || defined(BSP_USING_PWM3) || \
1313
defined(BSP_USING_PWM4) || defined(BSP_USING_PWM5) || \
@@ -217,4 +217,4 @@ static int rt_hw_pwm_w_init(void)
217217
}
218218
INIT_BOARD_EXPORT(rt_hw_pwm_w_init);
219219

220-
#endif /* BSP_USING_PWM */
220+
#endif /* BSP_USING_PWM_W */

‎bsp/renesas/ra6w1-ek/rafw_cfg/fsp_cfg/bsp/board_cfg.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
/* generated configuration header file - do not edit */
22
#ifndef BOARD_CFG_H_
33
#define BOARD_CFG_H_
4+
#define BSP_CFG_RTOS (3)
45
#include "../../../ra/board/rrq61xxx_evb/board.h"
56
#endif /* BOARD_CFG_H_ */

‎bsp/renesas/ra6w1-ek/rafw_gen/bsp_clock_cfg.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
#define BSP_CFG_PLL_PERI_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* PLL_PERI Src: PLL */
2525
#define BSP_CFG_PLL_PERI_DIV (BSP_CLOCKS_PLL_PERI_CLOCK_DIV_1_6) /* PLL_PERI Div /6 */
2626
#define BSP_CFG_PERI_CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL_PERI) /* PERI_CLK Src: PLL */
27-
#define BSP_CFG_I2C1CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV1) /* I2C1 Div /1 */
28-
#define BSP_CFG_I2C2CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV1) /* I2C2 Div /1 */
27+
#define BSP_CFG_I2C1CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV2) /* I2C1 Div /2 */
28+
#define BSP_CFG_I2C2CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_DIV2) /* I2C2 Div /2 */
2929
#define BSP_CFG_WDOG_DIV (BSP_CLOCKS_WDOG_DIV_320) /* WDOG Div /320 */
3030
#endif /* BSP_CLOCK_CFG_H_ */

‎bsp/renesas/ra6w1-ek/rafw_gen/hal_data.c‎

Lines changed: 58 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -422,6 +422,31 @@ RA6W1_TIM_INSTANCE_DEFINE(7, TIM_W_TIM8, VECTOR_NUMBER_TIMW7_IRQ)
422422
#endif /* BSP_USING_TIM_W */
423423

424424
#ifdef BSP_USING_HW_I2C0
425+
426+
#if defined(BSP_I2C0_RATE_STANDARD)
427+
/* 100 kHz: tLOW=4.77 us, tHIGH=5.22 us */
428+
#define I2C0_MASTER_RATE I2C_MASTER_RATE_STANDARD
429+
#define I2C0_MASTER_SCL_LCNT 187
430+
#define I2C0_MASTER_SCL_HCNT 205
431+
432+
#elif defined(BSP_I2C0_RATE_FAST)
433+
/* 400 kHz: tLOW=1.38 us, tHIGH=1.14 us */
434+
#define I2C0_MASTER_RATE I2C_MASTER_RATE_FAST
435+
#define I2C0_MASTER_SCL_LCNT 51
436+
#define I2C0_MASTER_SCL_HCNT 41
437+
438+
#elif defined(BSP_I2C0_RATE_FASTPLUS)
439+
/* 1 MHz: tLOW=580 ns, tHIGH=448 ns */
440+
#define I2C0_MASTER_RATE I2C_MASTER_RATE_FASTPLUS
441+
#define I2C0_MASTER_SCL_LCNT 19
442+
#define I2C0_MASTER_SCL_HCNT 13
443+
444+
#elif defined(BSP_I2C0_RATE_HIGHSPEED)
445+
#error "40 MHz I2C source cannot generate 3.4 MHz with the minimum HCNT/LCNT"
446+
#else
447+
#error "Select one BSP_I2C0_RATE_xxx option"
448+
#endif
449+
425450
i2c_master_w_instance_ctrl_t g_i2c_master0_ctrl;
426451

427452
const i2c_master_w_extended_cfg_t g_i2c_master0_extend =
@@ -437,15 +462,15 @@ const i2c_master_w_extended_cfg_t g_i2c_master0_extend =
437462
.gen_irq = FSP_INVALID_VECTOR,
438463
#endif
439464
.gen_ipl = 12,
440-
/* Actual calculated bitrate: 399600. Actual calculated duty cycle: 50%. Frequency of the selected clock source: 80000000. */
441-
.clock_settings.scl_lcnt = 100,
442-
.clock_settings.scl_hcnt = 93,
465+
466+
.clock_settings.scl_lcnt = I2C0_MASTER_SCL_LCNT,
467+
.clock_settings.scl_hcnt = I2C0_MASTER_SCL_HCNT,
443468
};
444469

445470
const i2c_master_cfg_t g_i2c_master0_cfg =
446471
{
447472
.channel = 1 - I2C_MASTER_W_CHANNEL_OFFSET,
448-
.rate = I2C_MASTER_RATE_FAST,
473+
.rate = I2C0_MASTER_RATE,
449474
.slave = 0x1D,
450475
.addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
451476
.p_transfer_tx = NULL,
@@ -485,6 +510,31 @@ const i2c_master_instance_t g_i2c_master0 =
485510
#endif
486511

487512
#ifdef BSP_USING_HW_I2C1
513+
514+
#if defined(BSP_I2C1_RATE_STANDARD)
515+
/* 100 kHz: tLOW=4.77 us, tHIGH=5.22 us */
516+
#define I2C1_MASTER_RATE I2C_MASTER_RATE_STANDARD
517+
#define I2C1_MASTER_SCL_LCNT 187
518+
#define I2C1_MASTER_SCL_HCNT 205
519+
520+
#elif defined(BSP_I2C1_RATE_FAST)
521+
/* 400 kHz: tLOW=1.38 us, tHIGH=1.14 us */
522+
#define I2C1_MASTER_RATE I2C_MASTER_RATE_FAST
523+
#define I2C1_MASTER_SCL_LCNT 51
524+
#define I2C1_MASTER_SCL_HCNT 41
525+
526+
#elif defined(BSP_I2C1_RATE_FASTPLUS)
527+
/* 1 MHz: tLOW=580 ns, tHIGH=448 ns */
528+
#define I2C1_MASTER_RATE I2C_MASTER_RATE_FASTPLUS
529+
#define I2C1_MASTER_SCL_LCNT 19
530+
#define I2C1_MASTER_SCL_HCNT 13
531+
532+
#elif defined(BSP_I2C1_RATE_HIGHSPEED)
533+
#error "40 MHz I2C source cannot generate 3.4 MHz with the minimum HCNT/LCNT"
534+
#else
535+
#error "Select one BSP_I2C1_RATE_xxx option"
536+
#endif
537+
488538
i2c_master_w_instance_ctrl_t g_i2c_master1_ctrl;
489539

490540
const i2c_master_w_extended_cfg_t g_i2c_master1_extend =
@@ -500,15 +550,15 @@ const i2c_master_w_extended_cfg_t g_i2c_master1_extend =
500550
.gen_irq = FSP_INVALID_VECTOR,
501551
#endif
502552
.gen_ipl = 12,
503-
/* Actual calculated bitrate: 399600. Actual calculated duty cycle: 50%. Frequency of the selected clock source: 80000000. */
504-
.clock_settings.scl_lcnt = 100,
505-
.clock_settings.scl_hcnt = 93,
553+
554+
.clock_settings.scl_lcnt = I2C1_MASTER_SCL_LCNT,
555+
.clock_settings.scl_hcnt = I2C1_MASTER_SCL_HCNT,
506556
};
507557

508558
const i2c_master_cfg_t g_i2c_master1_cfg =
509559
{
510560
.channel = 2 - I2C_MASTER_W_CHANNEL_OFFSET,
511-
.rate = I2C_MASTER_RATE_FAST,
561+
.rate = I2C1_MASTER_RATE,
512562
.slave = 0x1D,
513563
.addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
514564
.p_transfer_tx = NULL,

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