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GwenTheKweenGwenTheKween
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Merge pull request #11 from PPC64/billionai-next
Implemented VSX splat instructions
2 parents 8c33cea + 814a485 commit 4bb915d

6 files changed

Lines changed: 123 additions & 35 deletions

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‎target/ppc/insn32.decode‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,15 @@
4343
&X_bfl bf l:bool ra rb
4444
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
4545

46+
&X_imm8 xt imm:uint8_t
47+
%x_imm8_xt 0:1 21:5
48+
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_imm8_xt
49+
50+
&XX2 xt xb uim:uint8_t
51+
%xx2_xt 0:1 21:5
52+
%xx2_xb 1:1 11:5
53+
@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
54+
4655
### Fixed-Point Load Instructions
4756

4857
LBZ 100010 ..... ..... ................ @D
@@ -124,3 +133,8 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
124133
## Vector Bit Manipulation Instruction
125134

126135
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
136+
137+
## VSX splat instruction
138+
139+
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
140+
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2

‎target/ppc/insn64.decode‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,18 @@
2424
...... rt:5 ra:5 ................ \
2525
&PLS_D si=%pls_si
2626

27+
# Format 8RR:D
28+
%8rr_si 32:s16 0:16
29+
%8rr_xt 16:1 21:5
30+
&8RR_D_IX xt ix si:int32_t
31+
@8RR_D_IX ...... .. .... .. .. ................ \
32+
...... ..... ... ix:1 . ................ \
33+
&8RR_D_IX si=%8rr_si xt=%8rr_xt
34+
&8RR_D xt si:int32_t
35+
@8RR_D ...... .. .... .. .. ................ \
36+
...... ..... .... . ................ \
37+
&8RR_D si=%8rr_si xt=%8rr_xt
38+
2739
### Fixed-Point Load Instructions
2840

2941
PLBZ 000001 10 0--.-- .................. \
@@ -61,6 +73,15 @@ PADDI 000001 10 0--.-- .................. \
6173
PLFS 000001 10 0--.-- .................. \
6274
110000 ..... ..... ................ @PLS_D
6375

76+
### VSX instructions
77+
78+
XXSPLTIDP 000001 01 0000 -- -- ................ \
79+
100000 ..... 0010 . ................ @8RR_D
80+
XXSPLTIW 000001 01 0000 -- -- ................ \
81+
100000 ..... 0011 . ................ @8RR_D
82+
XXSPLTI32DX 000001 01 0000 -- -- ................ \
83+
100000 ..... 000 .. ................ @8RR_D_IX
84+
6485
### Prefixed No-operation Instruction
6586

6687
@PNOP 000001 11 0000-- 000000000000000000 \

‎target/ppc/translate.c‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7477,6 +7477,22 @@ static int times_4(DisasContext *ctx, int x)
74777477
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
74787478
#endif
74797479

7480+
#define REQUIRE_VECTOR(CTX) \
7481+
do { \
7482+
if (unlikely(!(CTX)->altivec_enabled)) { \
7483+
gen_exception((CTX), POWERPC_EXCP_VPU); \
7484+
return true; \
7485+
} \
7486+
} while (0)
7487+
7488+
#define REQUIRE_VSX(CTX) \
7489+
do { \
7490+
if(unlikely(!ctx->vsx_enabled)) { \
7491+
gen_exception(ctx, POWERPC_EXCP_VSXU); \
7492+
return true; \
7493+
} \
7494+
} while(0)
7495+
74807496
/*
74817497
* Helpers for implementing sets of trans_* functions.
74827498
* Defer the implementation of NAME to FUNC, with optional extra arguments.

‎target/ppc/translate/vector-impl.c.inc‎

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -17,20 +17,12 @@
1717
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
1818
*/
1919

20-
#define REQUIRE_ALTIVEC(CTX) \
21-
do { \
22-
if (unlikely(!(CTX)->altivec_enabled)) { \
23-
gen_exception((CTX), POWERPC_EXCP_VPU); \
24-
return true; \
25-
} \
26-
} while (0)
27-
2820
static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2921
{
3022
TCGv_i64 tgt, src, mask;
3123

3224
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
33-
REQUIRE_ALTIVEC(ctx);
25+
REQUIRE_VECTOR(ctx);
3426

3527
tgt = tcg_temp_new_i64();
3628
src = tcg_temp_new_i64();

‎target/ppc/translate/vsx-impl.c.inc‎

Lines changed: 71 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1569,47 +1569,94 @@ static void gen_xxsel(DisasContext *ctx)
15691569
vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
15701570
}
15711571

1572-
static void gen_xxspltw(DisasContext *ctx)
1572+
static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
15731573
{
1574-
int rt = xT(ctx->opcode);
1575-
int rb = xB(ctx->opcode);
1576-
int uim = UIM(ctx->opcode);
15771574
int tofs, bofs;
15781575

1579-
if (unlikely(!ctx->vsx_enabled)) {
1580-
gen_exception(ctx, POWERPC_EXCP_VSXU);
1581-
return;
1582-
}
1576+
REQUIRE_VSX(ctx);
15831577

1584-
tofs = vsr_full_offset(rt);
1585-
bofs = vsr_full_offset(rb);
1586-
bofs += uim << MO_32;
1578+
tofs = vsr_full_offset(a->xt);
1579+
bofs = vsr_full_offset(a->xb);
1580+
bofs += a->uim << MO_32;
15871581
#ifndef HOST_WORDS_BIG_ENDIAN
15881582
bofs ^= 8 | 4;
15891583
#endif
15901584

15911585
tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
1586+
return true;
15921587
}
15931588

15941589
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
15951590

1596-
static void gen_xxspltib(DisasContext *ctx)
1591+
static bool trans_XXSPLTIB(DisasContext *ctx, arg_XXSPLTIB *a)
15971592
{
1598-
uint8_t uim8 = IMM8(ctx->opcode);
1599-
int rt = xT(ctx->opcode);
1593+
if (a->xt < 32) {
1594+
REQUIRE_VSX(ctx);
1595+
} else {
1596+
REQUIRE_VECTOR(ctx);
1597+
}
1598+
tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(a->xt), 16, 16, a->imm);
1599+
return true;
1600+
}
16001601

1601-
if (rt < 32) {
1602-
if (unlikely(!ctx->vsx_enabled)) {
1603-
gen_exception(ctx, POWERPC_EXCP_VSXU);
1604-
return;
1605-
}
1602+
static bool trans_XXSPLTIW(DisasContext* ctx, arg_8RR_D *a)
1603+
{
1604+
REQUIRE_VSX(ctx);
1605+
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1606+
1607+
tcg_gen_gvec_dup_imm(MO_32, vsr_full_offset(a->xt), 16, 16, a->si);
1608+
1609+
return true;
1610+
}
1611+
1612+
static bool trans_XXSPLTIDP(DisasContext* ctx, arg_8RR_D *a)
1613+
{
1614+
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1615+
REQUIRE_VSX(ctx);
1616+
1617+
tcg_gen_gvec_dup_imm(MO_64, vsr_full_offset(a->xt), 16, 16, helper_todouble(a->si));
1618+
return true;
1619+
}
1620+
1621+
static bool trans_XXSPLTI32DX(DisasContext* ctx, arg_8RR_D_IX *a)
1622+
{
1623+
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1624+
REQUIRE_VSX(ctx);
1625+
1626+
TCGv_i64 new_val;
1627+
TCGv_i64 mask;
1628+
TCGv_i64 t0;
1629+
TCGv_i64 t1;
1630+
new_val = tcg_temp_new_i64();
1631+
mask = tcg_temp_new_i64();
1632+
t0 = tcg_temp_new_i64();
1633+
t1 = tcg_temp_new_i64();
1634+
1635+
get_cpu_vsrh(t0, a->xt);
1636+
get_cpu_vsrl(t1, a->xt);
1637+
1638+
tcg_gen_movi_i64(new_val, a->si);
1639+
if (a->ix) {
1640+
tcg_gen_movi_i64(mask, 0x00000000ffffffff);
1641+
tcg_gen_shli_i64(new_val, new_val, 32);
16061642
} else {
1607-
if (unlikely(!ctx->altivec_enabled)) {
1608-
gen_exception(ctx, POWERPC_EXCP_VPU);
1609-
return;
1610-
}
1643+
tcg_gen_movi_i64(mask, 0xffffffff00000000);
16111644
}
1612-
tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
1645+
tcg_gen_and_i64(t0, t0, mask);
1646+
tcg_gen_or_i64(t0, t0, new_val);
1647+
tcg_gen_and_i64(t1, t1, mask);
1648+
tcg_gen_or_i64(t1, t1, new_val);
1649+
1650+
set_cpu_vsrh(a->xt, t0);
1651+
set_cpu_vsrl(a->xt, t1);
1652+
1653+
1654+
tcg_temp_free_i64(mask);
1655+
tcg_temp_free_i64(new_val);
1656+
tcg_temp_free_i64(t1);
1657+
tcg_temp_free_i64(t0);
1658+
1659+
return true;
16131660
}
16141661

16151662
static void gen_xxsldwi(DisasContext *ctx)

‎target/ppc/translate/vsx-ops.c.inc‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -350,8 +350,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
350350
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
351351
GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
352352
GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
353-
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
354-
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
355353
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
356354
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
357355
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),

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