Package and Interface level information is missing

[nitinhariharan]

I am using HdlConvertor to parse SystemVerilog code, but I am not getting detailed information about packages or interfaces. I am using the 2017 version, but I only receive module-level information. Below is the code I am using:

import json
from hdlConvertor import HdlConvertor
from hdlConvertorAst.language import Language
from hdlConvertorAst.to.json import ToJson

Sample SystemVerilog code with package

sv_code = """
package my_package;
typedef enum logic [1:0] {
RED,
GREEN,
BLUE
} color_t;

function automatic logic [7:0] get_color_value(color_t color);
case (color)
RED: return 8'hFF0000;
GREEN: return 8'h00FF00;
BLUE: return 8'h0000FF;
default: return 8'h000000;
endcase
endfunction
endpackage

module my_module;
import my_package::*;

// ... (rest of the module code)
endmodule
"""

Initialize HdlConvertor

c = HdlConvertor()

Parse the SystemVerilog code

ast = c.parse_str(sv_code, Language.SYSTEM_VERILOG_2017, [])

Convert to JSON

tj = ToJson()
json_data = tj.visit_HdlContext(ast)

Print the JSON

print(json.dumps(json_data, sort_keys=True, indent=4, separators=(',', ': ')))
I would appreciate any help or suggestions on how to get detailed information about packages and interfaces.

[nitinhariharan]

I would appreciate any help or suggestions on how to get detailed information about packages and interfaces.
It will be very helpful!!

[Thomasb81]

Hello

The placeholder to enable the visit of interface and package is currently in the tool marked as "not implemented":

			NotImplementedLogger::print(
					"Source_textParser.visitDescription.package_declaration",
					o);

hdlConvertor/src/svConvertor/source_textParser.cpp

Line 72 in 3f0e5a9

auto o = ctx->interface_declaration();

hdlConvertor/src/svConvertor/source_textParser.cpp

Line 90 in 3f0e5a9

auto o = ctx->package_declaration();

PR are welcome.